Display panel, manufacturing method and display device

Patent metadata

Field	Value
Publication number	US-12256582-B2
Application number	US-202117770253-A
Country	US
Kind code	B2
Filing date	Jun 10, 2021
Priority date	Jun 17, 2020
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

The present disclosure provides a display panel, a manufacturing method thereof and a display device. The display panel includes: a base substrate including a display region, a wiring region surrounding the display region and a bonding region located at a side of the display region; a light-emitting element arranged in the display region and including a cathode; and a first line and at least one second line in the wiring region, the first line being coupled to the cathode of the light-emitting element, two ends of the second line being coupled to the first line in the bonding region, and the first line and the second line being coupled through at least two via holes at an opposite side of the bonding region.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate, comprising a display region, a wiring region surrounding the display region and a bonding region, and the bonding region being located at a side of the display region;
a light-emitting element arranged in the display region and comprising a cathode;
a first line and at least one second line in the wiring region, the first line being coupled to the cathode of the light-emitting element, two ends of the second line being coupled to the first line in the bonding region, and the first line and the second line being coupled through at least two via holes at an opposite side of the bonding region; and
a touch layer located on the light-emitting element, wherein the second line is arranged at a same layer and made of a same material as the touch layer, and the touch layer and the second line are forming simultaneously with a same mask through a single patterning process.

2. The display panel according to claim 1 , further comprising two first PINs in the bonding region, wherein the two first PINs are coupled to the two ends of the second line respectively during an aging test, and a voltage applied through the two first PINs is the same as a voltage applied to the first line.

3. The display panel according to claim 2 , further comprising two second PINs in the bonding region, wherein the second PIN is configured to apply a voltage to the first line during the aging test.

4. The display panel according to claim 1 , wherein a part of an upper surface of the first line in the wiring region at the opposite side of the bonding region is covered by a packaging layer, and the second line is coupled to a part of the first line not covered by the packaging layer.

5. The display panel according to claim 1 , wherein the second line in other wiring regions except a side where the bonding region is located and the opposite side of the bonding region is arranged at a same layer as the first line and is located at a side of the first line away from the display region.

6. The display panel according to claim 1 , wherein the second line in other wiring regions except a side where the bonding region is located and the opposite side of the bonding region is arranged at a different layer from the first line.

7. The display panel according to claim 1 , wherein the at least two via holes are spaced apart from each other equally in the wiring region at the opposite side of the bonding region.

8. The display panel according to claim 1 , wherein the first line is a VSS line.

9. A display device, comprising the display panel according to claim 1 .

10. The display device according to claim 9 , wherein the display device further comprises two first PINs in the bonding region, wherein the two first PINs are coupled to the two ends of the second line respectively during an aging test, and a voltage applied through the two first PINs is the same as a voltage applied to the first line.

11. The display device according to claim 10 , wherein the display device further comprises two second PINs in the bonding region, wherein the second PIN is configured to apply a voltage to the first line during the aging test.

12. The display device according to claim 9 , wherein a part of an upper surface of the first line in the wiring region at the opposite side of the bonding region is covered by a packaging layer, and the second line is coupled to a part of the first line not covered by the packaging layer.

13. The display device according to claim 9 , wherein the second line in other wiring regions except a side where the bonding region is located and the opposite side of the bonding region is arranged at a same layer as the first line and is located at a side of the first line away from the display region.

14. The display device according to claim 9 , wherein the second line in other wiring regions except a side where the bonding region is located and the opposite side of the bonding region is arranged at a different layer from the first line.

15. A method for manufacturing a display panel, comprising:
providing a base substrate, the base substrate comprising a display region, a wiring region surrounding the display region and a bonding region, and the bonding region being located at a side of the display region;
forming a first line in the wiring region on the base substrate;
forming a light-emitting element in the display region at a side of the first line away from the base substrate, the light-emitting element comprising a cathode, and the first line being coupled to the cathode of the light-emitting element; and
forming at least one second line in the wiring region, two ends of the second line being coupled to the first line in the bonding region, and the first line and the second line being coupled through at least two via holes at an opposite side of the bonding region;
wherein the forming the at least one second line in the wiring region comprises forming a touch layer and the second line simultaneously with a same mask through a single patterning process.

16. The method according to claim 15 , wherein subsequent to forming the first line in the wiring region on the base substrate, the method further comprises forming a packaging layer at a side of the first line away from the base substrate; prior to forming the at least one second line in the wiring region, the method further comprises forming at least two via holes in the wiring region at the opposite side of the bonding region through a patterning process and forming a part of the first line not covered by the packaging layer; and the forming the at least one second line in the wiring region comprises forming the second line on the part of the first line not covered by the packaging layer.

17. The method according to claim 15 , wherein the at least two via holes are spaced apart from each other equally in the wiring region at the opposite side of the bonding region.

18. The manufacturing method of the display panel according to claim 15 , further comprising, after an aging test has been completed on the display panel, cutting off a layered structure comprising the second line of the display panel beyond a side where the bonding region is located and the opposite side of the bonding region to form a narrow-bezel display panel.

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Cheng Rui
• Zhang Yunpeng
• Sun Lele

Classifications

• H10H20/0364

  of interconnections · CPC title

• H10H20/01

  Manufacture or treatment · CPC title

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/40

  OLEDs integrated with touch screens · CPC title