On-die formation of single-crystal semiconductor structures

Patent metadata

Field	Value
Publication number	US-12256553-B2
Application number	US-202318144708-A
Country	US
Kind code	B2
Filing date	May 8, 2023
Priority date	Aug 9, 2021
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

Methods, systems, and devices for on-die formation of single-crystal semiconductor structures are described. In some examples, a layer of semiconductor material may be deposited above one or more decks of memory cells and divided into a set of patches. A respective crystalline arrangement of each patch may be formed based on nearly or partially melting the semiconductor material, such that nucleation sites remain in the semiconductor material, from which respective crystalline arrangements may grow. Channel portions of transistors may be formed at least in part by doping regions of the crystalline arrangements of the semiconductor material. Accordingly, operation of the memory cells may be supported by lower circuitry (e.g., formed at least in part by doped portions of a crystalline semiconductor substrate), and upper circuitry (e.g., formed at least in part by doped portions of a semiconductor deposited over the memory cells and formed with a crystalline arrangement in-situ).

First claim

What is claimed is:

1. An apparatus, comprising:
a deck of memory cells:
a dielectric portion above the deck of memory cells;
a semiconductor portion above the dielectric portion and comprising a plurality of single crystal patches each having a bottom surface in contact with a flat top surface of the dielectric portion; and
a plurality of transistors coupled with the deck of memory cells, wherein each transistor of the plurality of transistors comprises:
a first terminal in contact with a respective first doped portion of one of the plurality of single crystal patches;
a second terminal in contact with a respective second doped portion of the one of the plurality of single crystal patches; and
a gate conductor operable to modulate a conductivity of a respective third doped portion of the one of the plurality of single crystal patches that is between the respective first doped portion and the respective second doped portion.

2. The apparatus of claim 1 , wherein the plurality of transistors comprises:
a first set of multiple transistors each associated with a respective first doped portion of a first single crystal patch, a respective second doped portion of the first single crystal patch, and a respective third doped portion of the first single crystal patch; and
a second set of multiple transistors each associated with a respective first doped portion of a second single crystal patch, a respective second doped portion of the second single crystal patch, and a respective third doped portion of the second single crystal patch.

3. The apparatus of claim 1 , wherein the dielectric portion comprises silicon dioxide.

4. The apparatus of claim 3 , wherein the silicon dioxide has a thickness between 1 micrometer and 6 micrometers.

5. The apparatus of claim 1 , wherein each of the plurality of single crystal patches has a width between 2 micrometers and 4 micrometers.

6. The apparatus of claim 1 , wherein each of the plurality of single crystal patches has a square cross-sectional area.

7. The apparatus of claim 1 , wherein a width of the dielectric portion between single crystal patches of the plurality of single crystal patches is between 10 nanometers and 20 nanometers.

8. An apparatus, comprising:
a substrate;
a dielectric portion above the substrate;
a plurality of single-crystal semiconductor patches each in contact with a surface of the dielectric portion and extending from the surface along a direction away from the substrate; and
a plurality of transistors, wherein each transistor of the plurality of transistors comprises:
a respective channel portion comprising one or more doped portions of one of the plurality of single-crystal semiconductor patches;
a respective gate portion operable to modulate a conductivity through the respective channel portion; and
a respective gate dielectric between the respective gate portion and the respective channel portion.

9. The apparatus of claim 8 , wherein each transistor of the plurality of transistors is associated with:
a respective first terminal in contact with a respective first doped portion of the one of the plurality of single-crystal semiconductor patches; and
a respective second terminal in contact with a respective second doped portion of the one of the plurality of single-crystal semiconductor patches.

10. The apparatus of claim 8 , wherein the respective channel portion of each transistor of the plurality of transistors comprises:
a respective first doped portion of one of the plurality of single-crystal semiconductor patches;
a respective second doped portion of the one of the plurality of single-crystal semiconductor patches; and
a respective third doped portion of the one of the plurality of single-crystal semiconductor patches between the respective first doped portion and the respective second doped portion,
wherein the respective gate portion is operable to modulate a conductivity through the respective first doped portion, the respective second doped portion, and the respective third doped portion.

11. The apparatus of claim 8 , wherein the plurality of transistors comprises:
a first set of multiple transistors each associated with a respective first doped portion of a first single-crystal semiconductor patch, a respective second doped portion of the first single-crystal semiconductor patch, and a respective third doped portion of the first single-crystal semiconductor patch; and
a second set of multiple transistors each associated with a respective first doped portion of a second single-crystal semiconductor patch, a respective second doped portion of the second single-crystal semiconductor patch, and a respective third doped portion of the second single-crystal semiconductor patch.

12. The apparatus of claim 8 , wherein the dielectric portion comprises silicon dioxide.

13. The apparatus of claim 12 , wherein the silicon dioxide has a thickness between 1 micrometer and 6 micrometers.

14. The apparatus of claim 8 , wherein each of the plurality of single-crystal semiconductor patches has a width between 2 micrometers and 4 micrometers.

15. The apparatus of claim 8 , wherein each of the plurality of single-crystal semiconductor patches has a square cross-sectional area.

16. The apparatus of claim 8 , wherein a width of the dielectric portion between single-crystal semiconductor patches of the plurality of single-crystal semiconductor patches is between 10 nanometers and 20 nanometers.

17. The apparatus of claim 8 , further comprising:
a plurality of memory cells between the substrate and the dielectric portion, wherein at least a subset of the plurality of transistors is operable to support an access operation on the plurality of memory cells.

18. The apparatus of claim 8 , further comprising:
a plurality of second transistors each having a respective channel portion formed at least in part by a doped portion of the substrate, wherein at least a subset of the plurality of transistors is coupled with at least a subset of the plurality of second transistors.

Assignees

• Micron Technology Inc

Inventors

• Hull Jeffery Brandt
• Khandekar Anish A
• Liu Hung-Wei
• Chhajed Sameer

Classifications

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title

• H10P14/3438

  Doping during depositing · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3238 Primary

  being insulating materials · CPC title