Generalized LDPC encoder, generalized LDPC encoding method and storage device

Patent metadata

Field	Value
Publication number	US-12255666-B2
Application number	US-202318225313-A
Country	US
Kind code	B2
Filing date	Jul 24, 2023
Priority date	Oct 6, 2022
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A generalized low-density parity-check (G-LDPC) encoder, including a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure including information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders includes a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder includes a plurality of single check nodes configured to perform a single parity check, wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and wherein the LDPC encoder is configured to: obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders, determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and output the information bits, the inner parity bits, and the outer parity bits as a codeword.

First claim

What is claimed is:

1. A generalized low-density parity-check (G-LDPC) encoder comprising:
a plurality of generalized constraint (GC) encoders configured to perform a plurality of GC encoding operations in parallel based on a GC code having a quasi-cyclic (QC) structure comprising information variable nodes, inner parity variable nodes, and super check nodes configured to perform multiple condition checks, wherein each GC encoder of the plurality of GC encoders comprises a plurality of first logic circuits configured to perform a GC encoding operation of the plurality of GC encoding operations; and
an LDPC encoder configured to perform an LDPC encoding operation based on an LDPC code having the QC structure, wherein the LDPC encoder comprises a plurality of single check nodes configured to perform a single parity check,
wherein the each GC encoder is configured to receive information bits, and to determine parity bits of a portion of inner parity bits corresponding to the information bits by enabling only a portion of the plurality of first logic circuits to perform the GC encoding operation, and
wherein the LDPC encoder is configured to:
obtain the inner parity bits by combining the parity bits obtained from the plurality of GC encoders,
determine outer parity bits corresponding to the information bits and the inner parity bits by performing the LDPC encoding operation, and
output the information bits, the inner parity bits, and the outer parity bits as a codeword.

2. The G-LDPC encoder of claim 1 , wherein each first logic circuit of the plurality of first logic circuits comprises a plurality of variable node processors, a super check node processor, and
wherein a connection structure between the plurality of variable node processors and the super check node processor is based on a protograph of the GC code having the QC structure.

3. The G-LDPC encoder of claim 2 , wherein, in the each first logic circuit, the connection structure connects the super check node processor and all processors corresponding to the inner parity variable nodes from among the plurality of variable node processors.

4. The G-LDPC encoder of claim 2 , wherein the super check node processor is configured to perform a binary code operation comprising at least one of a BCH code operation or a Hamming code operation, or to perform a non-binary code operation.

5. The G-LDPC encoder of claim 1 , wherein the LDPC encoder comprises a plurality of second logic circuits configured to perform the LDPC encoding operation in parallel.

6. The G-LDPC encoder of claim 1 , wherein the plurality of GC encoders are configured to enable only the portion of the plurality of first logic circuits such that the inner parity bits are respectively connected to different super check nodes.

7. A generalized low-density parity-check (G-LDPC) encoding method, comprising:
generating a basic generalized constraint (GC) code parity check matrix (PCM) comprising information variable nodes, inner parity variable nodes, and a plurality of super check nodes configured to perform multiple condition checks;
generating a basic LDPC code PCM comprising the information variable nodes, the inner parity variable nodes, outer parity variable nodes, and a plurality of single check nodes configured to perform a single parity check;
concatenating the basic GC code PCM and the basic LDPC code PCM to generate a concatenated PCM;
generating a G-LDPC code PCM having a quasi-cyclic (QC) structure by lifting the concatenated PCM;
activating a portion of the plurality of super check nodes such that a number of super check nodes connected to each inner parity variable node is one (1) in the G-LDPC code PCM having the QC structure;
receiving information bits and generating inner parity bits corresponding to the information bits by performing a GC encoding operation based on the activated portion of the plurality of super check nodes;
generating outer parity bits corresponding to the information bits and the inner parity bits by performing an LDPC encoding operation based on the plurality of single check nodes; and
outputting the information bits, the inner parity bits and the outer parity bits as codewords.

8. The G-LDPC encoding method of claim 7 , wherein the generating of the basic GC code PCM comprises connecting the plurality of super check nodes to the inner parity variable nodes respectively.

9. The G-LDPC encoding method of claim 7 , wherein the generating of the basic GC code PCM comprises generating a parity column matrix such that all elements of the parity column matrix comprising columns corresponding to the inner parity variable nodes and rows corresponding to the plurality of super check nodes have a value of one (1).

10. The G-LDPC encoding method of claim 9 , wherein the generating of the G-LDPC code PCM having the QC structure comprises expanding the all elements of the parity column matrix of the GC code PCM into an identity matrix.

11. The G-LDPC encoding method of claim 10 , wherein the generating of the G-LDPC code PCM having the QC structure further comprises:
expanding each element of an information column matrix comprising columns corresponding to the information variable nodes of the basic LDPC code PCM and columns corresponding to the inner parity variable nodes of the basic LDPC code PCM into a first cyclic shifted identity matrix or a first zero matrix;
expanding a parity column matrix comprising columns corresponding to the outer parity variable nodes of the basic LDPC code PCM into a matrix having a dual-diagonal structure; and
expanding each element of an information column matrix comprising columns corresponding to the information variable nodes of the basic GC code PCM into a second cyclic shifted identity matrix or a second zero matrix.

12. The G-LDPC encoding method of claim 7 , wherein the generating of the basic GC code PCM comprises:
adopting a same coding scheme and a same code rate for the plurality of super check nodes; and
respectively connecting the plurality of super check nodes to the each inner parity variable node.

13. The G-LDPC encoding method of claim 7 , wherein the generating of the inner parity bits comprises performing respective operations corresponding to the activated portion of the plurality of super check nodes in parallel.

14. The G-LDPC encoding method of claim 13 , wherein the generating of the outer parity bits comprises performing respective operations corresponding to the plurality of single check nodes in parallel.

15. The G-LDPC encoding method of claim 7 , wherein the activating of the portion of the plurality of super check nodes comprises setting elements of rows corresponding to inactive nodes from among the plurality of super check nodes in the G-LDPC code PCM having the QC structure to zero (0).

16. The G-LDPC encoding method of claim 7 , wherein the activating of the portion of the plurality of super check nodes comprises:
indexing rows corresponding to super check nodes included in each super check node group lifted from plurality of the super check nodes of the basic GC code;
selecting rows having different indices from the each super check node group; and
activating only the selected rows.

17. A storage device comprising:
a storage controller configured to:
receive information bits,
generate parity bits for the information bits by performing a generalized low density parity check (G-LDPC) encoding operation based on a G-LDPC code having a quasi-cyclic (QC) structure, and
output the information bits and the parity bits as a codeword; and

a non-vola

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Daeyeol
• Jun Bohwan
• Son Hongrak
• Yu Geunyeong
• Hwang Youngjun

Classifications

• H03M13/6563

  Implementations using multi-port memories · CPC title

• H03M13/616

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/1137 Primary

  Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel · CPC title

• H03M13/1102 Primary

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title