DA converter circuit, electro-optical device, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-12254840-B2
Application number	US-202418592413-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Mar 2, 2023
Publication date	Mar 18, 2025
Grant date	Mar 18, 2025

Abstract

A DA converter circuit includes an upper DA converter circuit that includes a first capacitance element including one end coupled to a data line and that outputs a voltage corresponding to five high-order bits to the data line, a lower DA converter circuit that includes a second capacitance element including one end coupled to a relay line and that outputs a voltage corresponding to five low-order bits to the relay line, and a capacitor including one end coupled to the relay line and the other end coupled to the data line. In the first capacitance element, an insulating layer is sandwiched between a first electrode and a second electrode. In the second capacitance element, an insulating layer is sandwiched between a third electrode and a fourth electrode. The insulating layer of the first capacitance element is thicker than the insulating layer of the second capacitance element.

First claim

What is claimed is:

1. A DA converter circuit comprising:
a first DA converter circuit including a first capacitance element, the first DA converter circuit being configured to output a voltage corresponding to a high-order bit of a plurality of bits to a first data line;
a second DA converter circuit including a second capacitance element, the second DA converter circuit being configured to output a voltage corresponding to a low-order bit of the plurality of bits to a second data line; and
a coupling capacitor including one end coupled to the second data line and the other end coupled to the first data line, wherein
the first capacitance element includes
a first electrode electrically coupled to the first data line,
a second electrode, and
a first insulating layer provided between the first electrode and the second electrode, and

the second capacitance element includes
a third electrode electrically coupled to the second data line,
a fourth electrode, and
a second insulating layer provided between the third electrode and the fourth electrode and having a thickness smaller than a thickness of the first insulating layer.

2. The DA converter circuit according to claim 1 , wherein
the first capacitance element is provided corresponding to one bit of the high-order bits,
the second capacitance element is provided corresponding to one bit of the low-order bits,
a low-amplitude logic signal corresponding to the one bit of the high-order bits is converted into a high-amplitude logic signal by a level shifter and supplied to the other end of the first capacitance element, and
a low-amplitude logic signal corresponding to the one bit of the low-order bits is supplied to the other end of the second capacitance element.

3. The DA converter circuit according to claim 2 , wherein
a withstand voltage of a transistor configured to select and supply a high level of the low-amplitude logic signal or a low level of the low-amplitude logic signal to the other end of the second capacitance element is lower than a withstand voltage of a transistor configured to select and supply a high level of the high-amplitude logic signal or a low level of the high-amplitude logic signal to the other end of the first capacitance element.

4. The DA converter circuit according to claim 3 , wherein
a difference between the high level of the high-amplitude logic signal and the low level of the high-amplitude logic signal is different from a difference between the high level of the low-amplitude logic signal and the low level of the low-amplitude logic signal.

5. The DA converter circuit according to claim 4 , wherein
the low level of the high-amplitude logic signal and the low level of the low-amplitude logic signal are common.

6. The DA converter circuit according to claim 4 , wherein
the low level of the high-amplitude logic signal and the high level of the low-amplitude logic signal are common.

7. An electro-optical device comprising:
the DA converter circuit according to claim 1 ;
a scanning line; and
a pixel circuit provided corresponding to the scanning line and the first data line, and including an electro-optical element configured to have brightness corresponding to a potential of the first data line in a writing period of a horizontal scanning period in which the scanning line is selected.

8. An electronic apparatus comprising:
the electro-optical device according to claim 7 .

Assignees

• Seiko Epson Corp

Inventors

• Ota Hitoshi

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0828

  forming a digital to analog [D/A] conversion circuit · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/3275 Primary

  Details of drivers for data electrodes · CPC title

• G09G3/36

  using liquid crystals · CPC title