Phase locked loop assisted fast start-up apparatus and method

Patent metadata

Field	Value
Publication number	US-12249997-B2
Application number	US-202117338497-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Jun 3, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

An apparatus and method are provided to re-configure an existing low-jitter phase locked loop (PLL) circuit for fast start-up during system wake-up. During system start-up, a feed-back path of the PLL is disconnected to independently control the VCO frequency. This independently controlled VCO then injects energy into a resonator (e.g., a crustal oscillator) for its fast start-up. Once a resonance frequency of the resonator is detected and an oscillation builds up in the resonator, a VCO control voltage is stored. The PLL feedback is then restored and the stored VCO control voltage is applied to perform phase-locking operation. Since the PLL control voltage is already set to the desired operating point, the PLL lock time is very small.

First claim

What is claimed is:

1. An apparatus comprising:
a resonator;
a phase locked loop (PLL) coupled to the resonator; and
a plurality of switches to operate the PLL in open loop during a configuration phase to determine a target oscillating frequency setting of the PLL, wherein the open loop of the PLL is coupled to the resonator to provide it with energy from an oscillator of the PLL during the configuration phase.

2. The apparatus of claim 1 , wherein the resonator comprises an oscillator coupled to an inverter, wherein an output of the oscillator is a reference clock which is provided to the PLL via a first switch of the plurality of switches.

3. The apparatus of claim 2 , wherein the oscillator of the resonator is a crystal oscillator.

4. The apparatus of claim 2 comprises logic to open the first switch during the configuration phase.

5. The apparatus of claim 1 comprises a generator to generate an oscillating frequency setting for the oscillator of the PLL during the configuration phase, wherein the oscillating frequency setting is provided via a second switch of the plurality of switches.

6. The apparatus of claim 5 comprises a third switch which disables normal control of the oscillator of the PLL during the configuration phase, wherein the normal control is generated by a closed loop operation of the PLL, wherein the third switch is of the plurality of switches.

7. The apparatus of claim 6 , wherein the plurality of switches causes the PLL to operate in closed loop during a frequency synthesis phase, wherein a last saved oscillating frequency setting is provided to the oscillator of the PLL when at a start of the frequency synthesis phase.

8. The apparatus of claim 5 , wherein the oscillator of the PLL is one of: a voltage-controlled oscillator, an LC-tank based oscillator, or a digitally controlled oscillator.

9. The apparatus of claim 1 comprises a resonance detector to monitor an output of the resonator and to detect an impedance change of resonator.

10. The apparatus of claim 9 wherein the resonance detector is to cause the plurality of switches to operate the PLL is a closed loop after the impedance change of resonator is detected.

11. The apparatus of claim 1 , wherein the PLL is one of an analog PLL, a digital PLL, a mixed signal PLL, or an LC PLL.

12. The apparatus of claim 1 , wherein an output of the PLL is used as an input clock for another PLL.

13. An apparatus comprising:
a phase locked loop (PLL) having a PLL oscillator;
a resonator coupled to the PLL; and
a circuitry to operate the PLL in an open loop and to inject energy from the PLL oscillator to the resonator during a configuration phase, and to operate the PLL in a closed loop after an impedance change of the resonator is detected.

14. The apparatus of claim 13 , comprises a generator to generate an oscillating frequency setting for the PLL oscillator during the configuration phase, wherein the oscillating frequency setting is provided via a first switch of a plurality of switches.

15. The apparatus of claim 14 comprises a second switch which disables normal control of the PLL oscillator during the configuration phase, wherein the normal control is generated by the closed loop operation of the PLL, wherein the second switch is of the plurality of switches.

16. The apparatus of claim 15 , wherein the plurality of switches causes the PLL to operate in closed loop during a frequency synthesis phase, wherein a last saved oscillating frequency setting is provided to the PLL oscillator when at a start of the frequency synthesis phase.

17. A system comprising:
a memory to store one or more instructions;
a processor circuitry to execute the one or more instructions, the processor circuitry coupled to the memory;
a wireless interface to allow the processor circuitry to communicate with another device,
wherein the processor circuitry includes:
a phase locked loop (PLL) coupled to a resonator; and
a plurality of switches to operate the PLL in open loop during a configuration phase to determine a target oscillating frequency setting of the PLL,
wherein the open loop of the PLL is coupled to the resonator to provide it with energy from an oscillator of the PLL during the configuration phase.

18. The system of claim 17 , wherein the resonator is off-die.

19. The system of claim 17 , wherein the processor circuitry comprises a generator to generate an oscillating frequency setting for the oscillator of the PLL during the configuration phase, wherein the oscillating frequency setting is provided via a second switch of the plurality of switches, wherein the plurality of switches includes a third switch which disables normal control of the oscillator during the configuration phase, wherein the normal control is generated by a closed loop operation of the PLL.

20. The system of claim 19 , wherein the plurality of switches causes the PLL to operate in closed loop during a frequency synthesis phase, wherein a last saved oscillating frequency setting is provided to the oscillator of the PLL when at a start of the frequency synthesis phase.

Assignees

• Intel Corp

Inventors

• Kundu Somnath
• Luo Hao
• Carlton Brent

Classifications

• H03L3/00

  Starting of generators · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/12 Primary

  using a scanning signal · CPC title