Nanorod light emitting device, substrate structure including a plurality of nanorod light emitting devices, and method of manufacturing the substrate structure

Patent metadata

Field	Value
Publication number	US-12249671-B2
Application number	US-202217582172-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Jun 22, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Provided is a substrate structure including a substrate, a buffer layer disposed on the substrate, a porous semiconductor layer disposed on the buffer layer, the porous semiconductor layer having a plurality of voids, a plurality of semiconductor light emitting structures disposed on the porous semiconductor layer, the plurality of semiconductor light emitting structures having a nanorod shape extending vertically, and a passivation film disposed on a side wall of each of the plurality of semiconductor light emitting structures, the passivation film having an insulation property.

First claim

What is claimed is:

1. A substrate structure comprising:
a substrate;
a buffer layer disposed on the substrate;
a porous semiconductor layer disposed on the buffer layer, the porous semiconductor layer having a plurality of voids;
a plurality of semiconductor light emitting structures disposed on the porous semiconductor layer, the plurality of semiconductor light emitting structures having a nanorod shape and extending vertically;
a planarization layer disposed between the porous semiconductor layer and the plurality of semiconductor light emitting structures; and
a passivation film disposed on entire sidewalls of each of the plurality of semiconductor light emitting structures, the passivation film having an insulation property,
wherein lower portions of the plurality of semiconductor light emitting structures extend horizontally along an upper surface of the planarization layer such that lower portions of the plurality of semiconductor light emitting structures are connected to each other.

2. The substrate structure of claim 1 , wherein each of the plurality of semiconductor light emitting structures comprises:
a first semiconductor layer disposed on the porous semiconductor layer and doped with an impurity of a first conductivity type;
a light emitting layer disposed on the first semiconductor layer and having a multi-quantum well structure;
a second semiconductor layer disposed on the light emitting layer and doped with an impurity of a second conductivity type that is electrically opposite to the first conductivity type; and
an electrode disposed on the second semiconductor layer.

3. The substrate structure of claim 2 , wherein the porous semiconductor layer is doped with the impurity of the first conductivity type.

4. The substrate structure of claim 2 , wherein a lower portion of the first semiconductor layer extends horizontally along an upper surface of the planarization layer such that lower portions of the first semiconductor layer of the plurality of semiconductor light emitting structures are connected to each other, and
wherein the passivation film extends over an upper surface of the first semiconductor layer between the plurality of semiconductor light emitting structures.

5. The substrate structure of claim 2 , wherein each of the plurality of semiconductor light emitting structures further comprises a superlattice layer disposed between the first semiconductor layer and the light emitting layer, and
wherein the superlattice layer comprises:
a plurality of first layers including a same material as a material of the first semiconductor layer; and
a plurality of second layers including a same material as a material of the light emitting layer, the plurality of second layer being alternately stacked with the plurality of first layers.

6. The substrate structure of claim 1 , wherein each of the plurality of semiconductor light emitting structures has a height ranging from 1 μm to 20 μm, and a diameter ranging from 0.05 μm to 1 μm.

7. The substrate structure of claim 1 , wherein the porous semiconductor layer and the planarization layer include a same semiconductor material, and
wherein the porous semiconductor layer is doped with an impurity of a first conductivity type, and the planarization layer is not doped or doped with the impurity of the first conductivity type with a doping concentration lower than a doping concentration of the porous semiconductor layer.

8. The substrate structure of claim 7 , wherein the doping concentration of the porous semiconductor layer ranges from 10 18 cm −3 to 10 20 cm −3 , and the doping concentration of the planarization layer ranges from 0 cm −3 to 10 16 cm −3 .

9. The substrate structure of claim 1 , further comprising a semiconductor crystal layer disposed between the buffer layer and the porous semiconductor layer,
wherein the porous semiconductor layer and the semiconductor crystal layer include a same semiconductor material, and
wherein the porous semiconductor layer is doped with an impurity of a first conductivity type, and the semiconductor crystal layer is undoped.

10. The substrate structure of claim 1 , wherein the porous semiconductor layer comprises a plurality of first porous semiconductor layers having a plurality of voids and a plurality of second porous semiconductor layers without voids, and
wherein the plurality of second porous semiconductor layers are alternately stacked with the plurality of first porous semiconductor layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Junhee
• Kim Nakhyun
• Kim Joosung
• Lee Eunsung
• Han Joohun
• Kong Kiho
• Park Junghun

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/819

  characterised by their shape, e.g. curved or truncated substrates · CPC title

• H10H20/812

  within the light-emitting regions, e.g. having quantum confinement structures · CPC title

• H10H20/034

  of coatings · CPC title

• H10H20/018

  Bonding of wafers · CPC title