Cap structure for interconnect dielectrics and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12249577-B2
Application number	US-202017125680-A
Country	US
Kind code	B2
Filing date	Dec 17, 2020
Priority date	Dec 17, 2020
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

An integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures, a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, the cap structure includes a top surface and a sidewall surface and a liner comprising a third dielectric on the top surface and on the sidewall surface.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first interconnect level comprising a first dielectric between a pair of interconnect structures comprising uppermost surfaces; and
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a cap structure comprising a second dielectric over the first dielectric, the cap structure comprising a top surface and a sidewall surface;
a liner comprising a third dielectric on the top surface and on the sidewall surface, but absent from at least a portion of the uppermost surfaces; and
a fourth dielectric over at least a portion of the liner and over the portion of the uppermost surfaces.

2. The integrated circuit structure of claim 1 , wherein the first dielectric comprises silicon, oxygen and a trace amount of less than 1 atomic percent of carbon, and wherein the second dielectric comprises silicon and oxygen.

3. The integrated circuit structure of claim 2 , wherein the second dielectric further comprises a trace amount of less than 1 atomic percent of aluminum.

4. The integrated circuit structure of claim 1 , wherein the third dielectric comprises oxygen and one of aluminum, hafnium, zirconium or titanium and wherein the liner has thickness between 0.7 nm and 2 nm.

5. The integrated circuit structure of claim 1 , wherein the liner is in contact with at least a second portion of the uppermost surfaces of individual ones of the pair of interconnect structures.

6. The integrated circuit structure of claim 1 , wherein the second dielectric has a vertical thickness as measured from an uppermost surface of the first dielectric, wherein the vertical thickness is between 3 nm and 6 nm.

7. The integrated circuit structure of claim 1 , wherein the cap structure extends onto at least a second portion of the uppermost surfaces of individual ones of the pair of interconnect structures, and wherein the liner is in contact with an uppermost surface of each interconnect.

8. The integrated circuit structure of claim 1 , wherein the cap structure has a first lateral thickness, wherein the liner has a second lateral thickness, and wherein the first dielectric has a third lateral thickness and wherein the third lateral thickness is equal to a combined sum of the first lateral thickness and two times a sum of the second lateral thickness.

9. The integrated circuit structure of claim 1 , wherein each of the pair of interconnect structures comprises a conductive liner adjacent the first dielectric and a fill metal on the conductive liner, and wherein the liner is over the conductive liner.

10. The integrated circuit structure of claim 1 , wherein the pair of interconnect structures is a first pair of interconnect structures and the second interconnect level further comprises:
a second pair of interconnect structures, wherein at least one of the second pair of interconnect structures is on at least some portion of a corresponding one of the first pair of interconnect structures; and
a fifth dielectric on the fourth dielectric and between the pair of second interconnect structures.

11. The integrated circuit structure of claim 10 , wherein a portion of the liner is in contact with the first pair of interconnect structures and the second pair of interconnect structures.

12. The integrated circuit structure of claim 10 , wherein the fourth dielectric is between the liner and the fifth dielectric, but not between the liner and the second pair of interconnect structures.

13. The integrated circuit structure of claim 10 , wherein the liner comprises a first portion between the cap structure and the fourth dielectric and a second portion between the cap structure and at least one interconnect structure in the second pair of interconnect structures, wherein the first portion of the liner comprises a first thickness and the second portion of the liner comprises a second thickness and wherein the second thickness is less than the first thickness.

14. The integrated circuit structure of claim 10 , wherein the fourth dielectric is between one of the second pair of interconnect structures and the fifth dielectric.

15. The integrated circuit structure of claim 1 , wherein the fourth dielectric is in direct contact with the portion of the uppermost surfaces.

16. A system comprising:
a processor;
a radio transceiver coupled to the processor, wherein the transceiver includes a transistor comprising:
a drain contact coupled to a drain;
a source contact coupled to a source; and
a gate contact coupled to a gate; and

an integrated circuit structure coupled with the drain contact, the integrated circuit structure comprising:
a first interconnect level comprising, a first dielectric adjacent a first interconnect structure;
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a cap structure comprising a second dielectric on the first dielectric, the cap structure comprising a top surface and a sidewall surface;
a liner comprising a third dielectric on the top surface and on the sidewall surface, but absent from at least a first portion of the first interconnect structure;
a second interconnect structure on at least a second portion of the first;
an etch stop layer comprising a fourth dielectric on least a portion of the liner and over at least the first portion of the first interconnect structure; and

and a fifth dielectric on the etch stop layer and adjacent the second interconnect structure; and
a memory device coupled with the second interconnect structure.

17. The system of claim 16 , further comprises a battery and an antenna coupled with the transistor, and wherein the memory device is a resistive random access memory device or a magnetic tunnel junction device.

18. The system of claim 16 , wherein the fourth dielectric is in direct contact with the first portion of the first interconnect structure.

19. An apparatus, comprising:
a first interconnect level comprising a first dielectric between a pair of first interconnect structures; and
a second interconnect level above the first interconnect level, the second interconnect level comprising:
a cap structure comprising a second dielectric over the first dielectric, the cap structure comprising a top surface and a sidewall surface;
a liner comprising a third dielectric on the top surface and on the sidewall surface;
a fourth dielectric on least a portion of the liner;
a fifth dielectric on the fourth dielectric and between a pair of second interconnect structures, wherein the fourth dielectric is between the liner and the fifth dielectric, but not between the liner and second pair of interconnect structures.

20. The apparatus of claim 19 , wherein the liner comprises a first portion between the cap structure and the fourth dielectric and a second portion between the cap structure and at least one of the second pair of interconnect structures, wherein the first portion comprises a first thickness and the second portion comprises a second thickness and wherein the second thickness is less than the first thickness.

Assignees

• Intel Corp

Inventors

• Vyas Shashi
• Naskar Sudipto
• Wallace Charles

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title