Semiconductor device, method of manufacturing the same and electronic device including the device

Patent metadata

Field	Value
Publication number	US-12249544-B2
Application number	US-202318317722-A
Country	US
Kind code	B2
Filing date	May 15, 2023
Priority date	Sep 30, 2016
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

First claim

I claim:

1. A semiconductor device, comprising:
a substrate;
a first device and a second device formed on the substrate, wherein each of the first device and the second device comprises:
a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence; and
a gate stack surrounding a periphery of the channel layer,

wherein the semiconductor device further comprises a first dielectric film formed on the first device and a second dielectric film formed on the second device, and the first dielectric film is in contact with the second dielectric film, and
wherein the first dielectric film is in contact with the second dielectric film in a direction parallel to a surface of the substrate, an orthogonal projection of the first dielectric film on the substrate overlaps at least partially with an orthogonal projection of the second dielectric film on the substrate.

2. The semiconductor device of claim 1 , wherein
an upper surface of the channel layer of the first device and an upper surface of the channel layer of the second device are co-planar; and/or
a lower surface of the channel layer of the first device and a lower surface of the channel layer of the second device are co-planar.

3. The semiconductor device of claim 1 , wherein a thickness of the channel layer of the first device is different from a thickness of the channel layer of the second device, or a channel length of the first device is different from a channel length of the second device.

4. The semiconductor device of claim 1 , further comprising:
gate contact pads extending from respective gate conductor layers in the respective gate stacks in a direction away from the respective channel layers, wherein the gate conductor layer and the corresponding gate contact pad of at least one of the first device and the second device comprise different materials.

5. The semiconductor device of claim 4 , wherein the gate contact pads of the first device and the second device comprise the same material.

6. The semiconductor device of claim 4 , wherein the gate conductor layer and the corresponding gate contact pad of the other of the first device and the second device comprise the same material and extend integrally.

7. The semiconductor device of claim 4 , wherein the gate contact pads of the first device and the second device are connected electrically to each other.

8. The semiconductor device of claim 7 , wherein the gate contact pads of the first device and the second device are directly connected physically to each other.

9. The semiconductor device of claim 1 , wherein each of the channel layers of the first device and the second device comprises a semiconductor material which is different from that of the corresponding first source/drain layer and the corresponding second source/drain layer.

10. The semiconductor device of claim 1 , wherein the channel layer comprises a channel layer single-crystalline semiconductor material.

11. The semiconductor device of claim 1 , wherein there is a doping distribution in end portions of the respective channel layers close to the first source/drain layers and the second source/drain layers.

12. The semiconductor device of claim 1 , further comprising:
an isolation layer formed on the substrate, wherein the isolation layer has a top surface at a level between top and bottom surfaces of the channel layer.

13. The semiconductor device of claim 1 , wherein for each of the first device and the second device, the first source/drain layer is a semiconductor layer epitaxially grown on the substrate, the channel layer is a semiconductor layer epitaxially grown on the first source/drain layer, the second source/drain layer is a semiconductor layer epitaxially grown on the channel layer, and there are crystal interfaces and/or doping concentration interfaces between the source/drain layers and the channel layer.

14. The semiconductor device of claim 1 , wherein for each of the first device and the second device, the channel layer has its periphery recessed inwards with respect to peripheries of the first source/drain layer and the second source/drain layer, and the gate stack is embedded into a recess which is formed by the periphery of the channel layer with respect to the peripheries of the first source/drain layer and the second source/drain layer.

15. The semiconductor device of claim 1 , wherein for each of the first device and the second device, the periphery of the channel layer protrudes outwards with respect to the peripheries of the first source/drain layer and the second source/drain layer.

16. The semiconductor device of claim 1 , wherein the first dielectric film is disposed on surfaces of the first source/drain layer and the second source/drain layer of the first device, and the second dielectric film is disposed on surfaces of the first source/drain layer and the second source/drain layer of the second device.

17. The semiconductor device of claim 1 , wherein the first dielectric film corresponds to the first device and is configured to generate compressive or tensile stress, and the second dielectric film corresponds to the second device and is configured to generate tensile or compressive stress.

18. The semiconductor device of claim 17 , wherein
the first device is an n-type device and the first dielectric film exhibits compressive stress in a direction perpendicular to a surface of the substrate, or the first dielectric film exhibits tensile stress in a direction perpendicular to a surface of the substrate in the channel layer of the n-type device; and
the second device is a p-type device and the second dielectric film exhibits tensile stress in the direction perpendicular to the surface of the substrate, or the second dielectric film exhibits compressive stress in the direction perpendicular to the surface of the substrate in the channel layer of the p-type device.

19. The semiconductor device of claim 1 ,
wherein in an overlapping region of the first dielectric film and the second dielectric film, a part of the first dielectric film is above a part of the second dielectric film; or in an overlapping region of the first dielectric film and the second dielectric film, a part of the second dielectric film is above a part of the first dielectric film.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Zhu Huilong

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P32/1406

  by ion implantation · CPC title