Interface circuit, memory controller and method for calibrating signal processing devices in an interface circuit

Patent metadata

Field	Value
Publication number	US-12249385-B2
Application number	US-202318225654-A
Country	US
Kind code	B2
Filing date	Jul 24, 2023
Priority date	Apr 25, 2023
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A method for calibrating a characteristic value of a signal processing device comprised in SerDes inside of an interface circuit of a memory controller includes: monitoring a current of a voltage of a test element to generate a process detection result by a monitor and calibration module; monitoring an environment temperature to generate a temperature monitored result by the monitor and calibration module; selecting a reference value subset from multiple reference value subsets as a preferred reference value subset for a calibration operation based on the process detection result and the temperature monitored result; and performing the calibration operation on the signal processing device by at least one calibration circuit of the monitor and calibration module according to the preferred reference value subset to adjust the characteristic value of the signal processing device.

First claim

What is claimed is:

1. An interface circuit, comprising:
a signal processing circuit, configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device,
wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a process monitor, configured to monitor a current or a voltage of a test element to generate a process detection result;
a temperature monitor, configured to monitor an environment temperature to generate a temperature monitored result;
a processor, configured to receive the process detection result and the temperature monitored result and select a reference value subset as a preferred reference value subset for a calibration operation from a plurality of reference value subsets based on the process detection result and the temperature monitored result; and
a calibration circuit, coupled to the processor and at least one of the plurality of signal processing devices and configured to perform the calibration operation on the at least one of the plurality of signal processing devices according to the preferred reference value subset and in response to a control signal issued by the processer, to adjust a characteristic value of the at least one of the plurality of signal processing devices.

2. The interface circuit of claim 1 , wherein the interface circuit is configured inside of a memory controller and the signal processing circuit is a Serializer-Deserializer (SerDes).

3. The interface circuit of claim 2 , wherein the processor is further configured to obtain a preset process parameter which is a first-level process parameter, determine a second-level process parameter according to the preset process parameter and the process detection result, and select the reference value subset as the preferred reference value subset according to the second-level process parameter and the temperature monitored result.

4. The interface circuit of claim 3 , wherein the first-level process parameter indicates a preliminary process corner classification and the second-level process parameter indicates an advanced process corner classification.

5. The interface circuit of claim 1 , wherein the calibration circuit is configured to set an initial value utilized by the at least one of the plurality of signal processing devices in the calibration operation based on a value in the preferred reference value subset.

6. The interface circuit of claim 1 , wherein the processor is configured to keep receiving a latest temperature monitored result and determine whether to re-perform the calibration operation according to the latest temperature monitored result, wherein when the calibration operation is determined to be re-performed, the processor is further configured to select another preferred reference value subset from the plurality of reference value subsets for re-performing the calibration operation based on the process detection result and the latest temperature monitored result.

7. The interface circuit of claim 1 , wherein after the calibration operation is completed, the processor is further configured to determine whether a difference between the characteristic value of the at least one of the plurality of signal processing devices and a corresponding value in the preferred reference value subset is greater than a threshold value, and when the difference is greater than the threshold value, the processor is further configured to modify a corresponding value in the reference value subset which was as selected the preferred reference value subset according to the difference.

8. A memory controller, coupled to a memory device to control access operations of the memory device, comprising:
a host interface, configured to communicate with a host device and comprising a signal processing circuit to process a reception signal received from the host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises:
a plurality of signal processing devices; and
a monitor and calibration module, comprising:
a process monitor, configured to monitor a current or a voltage of a test element to generate a process detection result;
a temperature monitor, configured to monitor an environment temperature to generate a temperature monitored result;
a processor, configured to receive the process detection result and the temperature monitored result and select a reference value subset as a preferred reference value subset for a calibration operation from a plurality of reference value subsets based on the process detection result and the temperature monitored result; and
a calibration circuit, coupled to the processor and at least one of the plurality of signal processing devices and configured to perform the calibration operation on the at least one of the plurality of signal processing devices according to the preferred reference value subset in response to a control signal issued by the processor to adjust a characteristic value of the at least one of the plurality of signal processing devices.

9. The memory controller of claim 8 , wherein the signal processing circuit is a Serializer-Deserializer (SerDes).

10. The memory controller of claim 8 , wherein the processor is further configured to obtain a preset process parameter which is a first-level process parameter, determine a second-level process parameter according to the preset process parameter and the process detection result, and select the reference value subset as the preferred reference value subset according to the second-level process parameter and the temperature monitored result.

11. The memory controller of claim 10 , wherein the first-level process parameter indicates a preliminary process corner classification and the second-level s parameter indicates an advanced process corner classification.

12. The memory controller of claim 8 , wherein the calibration circuit is configured to set an initial value utilized by the at least one of the plurality of signal processing devices in the calibration operation based on a value in the preferred reference value subset.

13. The memory controller of claim 8 , wherein the processor is configured to keep receiving a latest temperature monitored result and determine whether to re-perform the calibration operation according to the latest temperature monitored result, wherein when the calibration operation is determined to be re-performed, the processor is further configured to select another preferred reference value subset from the plurality of reference value subsets for re-performing the calibration operation based on the process detection result and the latest temperature monitored result.

14. The memory controller of claim 8 , wherein after the calibration operation is completed, the processor is further configured to determine whether a difference between the characteristic value of the at least one of the plurality of signal processing devices and a corresponding value in the preferred reference value subset is greater than a threshold value, and when the difference is greater than the threshold value, the processor is further configured to modify a corresponding value in the reference value subset which was selected as the preferred reference value subset according to the difference.

15. A method for calibrating characteristic values of a plurality of signal processing devices comprised in SerDes inside of an interface circuit of a memory controller, comprising:
monitoring a current or a voltage of a test element to generate a proce

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title