Open block-based read offset compensation in read operation of memory device

Patent metadata

Field	Value
Publication number	US-12249379-B2
Application number	US-202318387780-A
Country	US
Kind code	B2
Filing date	Nov 7, 2023
Priority date	Mar 11, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells arranged in blocks; and
a peripheral circuit coupled to the array of memory cells and configured to:
determine that a block of the blocks is an open block based on an open block information; and
in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage, wherein the compensated read voltage has an offset from a default read voltage of the block.

2. The memory device of claim 1 , wherein
each block of the blocks comprises pages; and
the open block information comprises an auto dynamic start voltage (ADSV) list comprising open blocks and a last programmed page of the pages of each open block.

3. The memory device of claim 2 , wherein the peripheral circuit is configured to determine that the block is an open block if the block is on the ADSV list.

4. The memory device of claim 1 , wherein the peripheral circuit is configured to update the open block information based on a program operation performed on the array of memory cells.

5. The memory device of claim 1 , wherein the peripheral circuit further comprises a register configured to store the open block information.

6. The memory device of claim 5 , wherein an initial open block information is stored from the array of memory cells into the register when initializing the open block information.

7. The memory device of claim 1 , wherein the open block information is collected from the array of memory cells.

8. The memory device of claim 2 , wherein to perform the read operation, the peripheral circuit is further configured to:
determine the compensated read voltage based on the open block information; and
apply the compensated read voltage to a word line coupled to the memory cell of the array of memory cells in the block.

9. The memory device of claim 8 , wherein the peripheral circuit is configured to:
determine the offset of the compensated read voltage from the default read voltage of the block based on the last programmed page.

10. The memory device of claim 9 , wherein the peripheral circuit is configured to calculate the offset based on the last programmed page and a total number of pages in the block.

11. The memory device of claim 9 , wherein
the pages in the block are separated into zones, the zones being associated with preset offsets, respectively, and
the peripheral circuit is configured to select the offset from the preset offsets based on one of the zones in which the last programmed page is in the block.

12. The memory device of claim 2 , wherein the peripheral circuit is further configured to:
determine that the block is a full block if the block is not on the ADSV list; and
in response to the block being the full block, perform a read operation on the memory cell of the array of memory cells in the block using the default read voltage of the block.

13. A memory system, comprising:
a memory device comprising:
an array of memory cells arranged in blocks; and
a peripheral circuit coupled to the array of memory cells and configured to:
determine that a block of the blocks is an open block based on an open block information; and
in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage, the compensated read voltage having an offset from a default read voltage of the block; and

a memory controller coupled to the memory device and configured to control the memory device.

14. The memory system of claim 13 , wherein to initiate the open block information, the memory controller is configured to, in response to system restart, scan the array of memory cells or restore a backup copy of the open block information.

15. A method for operating a memory device comprising an array of memory cells arranged in blocks, the method comprising:
determining that a block of the blocks is an open block based on an open block information; and
performing a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage, wherein the compensated read voltage having an offset from a default read voltage of the block.

16. The method of claim 15 , wherein:
each block of the blocks comprises a plurality of pages;
the open block information comprises an auto dynamic start voltage (ADSV) list comprising open blocks and a last programmed page of the pages of each open block; and
determining that a block of the blocks is an open block based on the open block information comprises:
determining that the block is an open block if the block is on the ADSV list.

17. The method of claim 15 , further comprising:
updating the open block information based on a program operation performed on the array of memory cells.

18. The method of claim 16 , wherein performing the read operation comprises:
calculating the offset based on the last programmed page and a total number of pages in the block;
determining the compensated read voltage based on the offset; and
applying the compensated read voltage to a word line coupled to the memory cell of the array of memory cells in the block.

19. The method of claim 15 , further comprising:
in response to system restart, scanning the array of memory cells or restoring a backup copy of the open block information.

20. The method of claim 16 , further comprising:
determining that the block is a full block if the block is not on the ADSV list; and
performing a read operation on the memory cell of the array of memory cells in the block based on the default read voltage of the block.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Guo Xiaojiang
• Kang Jong Hoon
• He Youxin

Classifications

• G11C16/30

  Power supply circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title