Single bitline SRAM pixel and method for driving the same

Patent metadata

Field	Value
Publication number	US-12249299-B2
Application number	US-202217962956-A
Country	US
Kind code	B2
Filing date	Oct 10, 2022
Priority date	Oct 10, 2022
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A novel bit storage circuit includes a first voltage supply line, a second voltage supply line, a bit line, a latch, a first switching transistor, and a blocking transistor. The latch includes an input and an output. The first switching transistor includes a first terminal, a second terminal, and a control terminal. The first switching transistor is operative to provide a conductive path and a non-conductive path between the bit line and the input of the latch responsive to a first control signal being asserted on the control terminal of the first switching transistor. The blocking transistor includes a control terminal and is operative to selectively provide a conductive path and a non-conductive path between the input of the latch and the second voltage supply line responsive to a second control signal. The blocking transistor facilitates the use of a single bit line.

First claim

We claim:

1. A bit storage circuit comprising:
a first voltage supply line;
a second voltage supply line;
a bit line;
a latch having an input and an output;
a first switching transistor having a first terminal, a second terminal, and a control terminal, said first switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a first control signal being asserted on said control terminal of said first switching transistor;
a blocking transistor including a control terminal and being operative to selectively provide a conductive path and a non-conductive path between said input of said latch and said second voltage supply line responsive to a second control signal; and
a second switching transistor having a first terminal, a second terminal, and a control terminal, said second switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a third control signal being asserted on said control terminal of said second switching transistor; and wherein
said first switching transistor and said second switching transistor are coupled in series between said bit line and said input of said latch; and
said bit storage circuit is connected to no more than one bit line.

2. The bit storage circuit of claim 1 , wherein said latch includes:
a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and
a second n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal selectively coupled to said input of said latch via said blocking transistor, and a gate terminal coupled to said output of said latch.

3. The bit storage circuit of claim 1 , wherein said latch includes:
a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and
a second n-channel transistor having a source terminal selectively coupled to said second voltage supply line via said blocking transistor, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch.

4. The bit storage circuit of claim 1 , further comprising a pixel electrode coupled to said output of said latch.

5. The bit storage circuit of claim 1 , wherein said bit storage circuit includes no more than seven transistors.

6. The bit storage circuit of claim 1 , further comprising a pulse generator having an output coupled to said control terminal of said blocking transistor.

7. The bit storage circuit of claim 1 , wherein said control terminal of said blocking transistor is coupled to a third voltage supply line having a constant voltage between a voltage of said first voltage supply line and a voltage of said second voltage supply line, whereby said second control signal is said constant voltage, and said blocking transistor is maintained in a partially conducting state.

8. A display comprising:
a first voltage supply line;
a second voltage supply line;
an array of pixel electrodes arranged in columns and rows;
a plurality of row enable lines;
a plurality of blocking signal lines;
a plurality of bit lines; and
an array of pixel circuits arranged in columns and rows; and wherein each of said pixel circuits includes
a latch having an input coupled to one of said bit lines and an output coupled to one of said pixel electrodes;
a first switching transistor having a control terminal coupled to one of said row enable lines, said first switching transistor being operative to provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a first control signal being asserted on said row enable line;
a blocking transistor including a control terminal coupled to one of said blocking signal lines and being operative to selectively provide a conductive path and a non-conductive path between said input of said latch and said second voltage supply line responsive to a second control signal asserted on said one of said blocking signal lines; and
a plurality of column enable lines; and wherein
each pixel includes a second switching transistor having a control terminal coupled to one of said column enable lines, said second switching transistor being operative to selectively provide a conductive path and a non-conductive path between said bit line and said input of said latch responsive to a third control signal being asserted on said one of said column enable lines;
said first switching transistor and said second switching transistor are coupled in series between said bit line and said input of said latch; and
each said pixel circuit is coupled to no more than one of said bit lines.

9. The display of claim 8 , wherein each of said latches includes:
a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and
a second n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal selectively coupled to said input of said latch via said blocking transistor, and a gate terminal coupled to said output of said latch.

10. The display of claim 8 , wherein each of said latches includes:
a first p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a first n-channel transistor having a source terminal coupled to said second voltage supply line, a drain terminal coupled to said output of said latch, and a gate terminal coupled to said input of said latch;
a second p-channel transistor having a source terminal coupled to said first voltage supply line, a drain terminal coupled to said input of said latch, and a gate terminal coupled to said output of said latch; and
a second n-channel transistor having a source terminal selectively coupled to said second voltage supply line via said blocking transistor, a drain terminal coupled to said input of said latch

Assignees

• Omnivision Tech Inc

Inventors

• Qin Qing
• Ryu Hoon

Classifications

• H10B10/12

  comprising a MOSFET load element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2320/041

  Temperature compensation · CPC title

• G09G2360/128

  Frame memory using a Synchronous Dynamic RAM [SDRAM] · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title