Stacked OLED microdisplay with low-voltage silicon backplane

Patent metadata

Field	Value
Publication number	US-12249278-B2
Application number	US-202117601202-A
Country	US
Kind code	B2
Filing date	Jan 26, 2021
Priority date	Jan 28, 2020
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A microdisplay comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein the light emitting OLED stack has three or more OLED units between a top electrode and a bottom electrode; and the control circuitry of the silicon-based backplane comprises at least two transistors with their channels connected in series between an external power source VDD, and the bottom electrode of the OLED stack. The light-emitting OLED stack preferably has a Vth of at least 7.5V or more. The control circuit can include a protection circuit comprised of a p-n diode, preferably a bipolar junction transistor.

First claim

The invention claimed is:

1. A microdisplay comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein:
the light emitting OLED stack has three or more OLED units between a top and a bottom electrode; and
the control circuitry of the silicon-based backplane comprises, for each individually addressable pixel, at least two transistors with their channels connected in series between an external power source V DD , and the bottom electrode of the OLED stack
where the transistors with their channels connected in series are both rated at 5V or lower.

2. The microdisplay of claim 1 wherein the Vth of the light emitting OLED stack is at least 7.5V or greater.

3. The microdisplay of claim 1 wherein the Vth of the light emitting OLED stack is at least 10V or greater.

4. The microdisplay of claim 1 wherein the OLED stack comprises four or more OLED light-emitting units.

5. The microdisplay of claim 1 wherein the OLED light-emitting units are each separated from each other by a charge-generation layer (CGL).

6. The microdisplay of claim 5 wherein the bottom electrode is segmented and each segment is in electrical contact with the control circuitry in the backplane.

7. The microdisplay of claim 6 wherein the OLED stack is top-emitting.

8. The microdisplay of claim 7 wherein the OLED stack forms a microcavity where the physical distance between the segmented bottom electrode and the top electrode is constant across all pixels.

9. A microdisplay comprising a light emitting OLED stack on top of a silicon-based backplane with individually addressable pixels and control circuitry wherein:
the light emitting OLED stack has three or more OLED units between a top and a bottom electrode; and
the control circuitry of the silicon-based backplane comprises, for each individually addressable pixel, at least two transistors with their channels connected in series between an external power source V DD , and the bottom electrode of the OLED stack

where the transistor closest to the power source is a driving transistor and is rated at 5V or lower and the transistor closest to the bottom electrode of the OLED is a switch transistor and is rated at greater than 5V.

10. The microdisplay of claim 1 wherein the two transistors with their channels connected in series are both p-channel transistors.

11. The microdisplay of claim 10 wherein the two transistors with their channels connected in series are each located in separate wells.

12. The microdisplay of claim 1 wherein the control circuitry additionally comprises a protection circuit comprising a p-channel transistor.

13. The microdisplay of claim 1 wherein the control circuitry additionally comprises a protection circuit comprising a p-n diode.

14. The microdisplay of claim 13 wherein the cathode of the p-n junction diode is connected to the node of the bottom electrode of the OLED stack and the anode is connected to a voltage reference V REF or a current reference I REF .

15. The microdisplay of claim 1 wherein the control circuitry additionally comprises a protection circuit comprising a bipolar junction transistor.

16. The microdisplay of claim 15 wherein the bipolar junction transistor is an NPN transistor wherein the base is connected either to a voltage source VPROTECT or a current source IPROTECT, the emitter is connected to a node connected to the bottom electrode of the OLED stack and the collector is connected to voltage source V DD .

17. The microdisplay of claim 15 wherein the base of the bipolar junction transistor is isolated, the emitter is connected to a node connected to the bottom electrode of the OLED stack and the collector is connected to voltage source V DD .

18. The microdisplay of claim 15 wherein the bipolar junction transistor is located in a separate well from the two transistors whose channels are connected in series.

19. The microdisplay of claim 18 wherein the two transistors with their channels connected in series are both p-channel transistors and are each located in separate n-wells and the bipolar junction transistor is a NPN transistor located in a separate p-well.

Assignees

• OLEDWorks LLC
• Fraunhofer Ges Forschung
• Fraunhofer Ges E V

Inventors

• Hamer John
• Kondakova Marina
• Spindler Jeffrey
• Richter Bernd
• Wartenberg Philipp
• Bunk Gerd
• Vogel Uwe

Classifications

• H10K59/876

  comprising a resonant cavity structure, e.g. Bragg reflector pair · CPC title

• G09G2330/04

  Display protection · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title