Pixel and display device including the same

Patent metadata

Field	Value
Publication number	US-12249268-B2
Application number	US-202217899382-A
Country	US
Kind code	B2
Filing date	Aug 30, 2022
Priority date	Dec 7, 2021
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

A pixel includes: first to fourth driving transistors; a first light emitting diode connected to the first driving transistor; a second light emitting diode connected to the second driving transistor and spaced apart from the first light emitting diode in a first direction; a third light emitting diode connected to the third driving transistor and disposed between the first light emitting diode and the second light emitting diode; and a fourth light emitting diode connected to the fourth driving transistor and disposed between the first light emitting diode and the second light emitting diode, wherein a planar area of the first driving transistor is smaller than a planar area of each of the third and fourth driving transistors, a planar area of the second driving transistor is smaller than a planar area of each of the third and fourth driving transistors, and a first data signal is applied to the first and second driving transistors.

First claim

What is claimed is:

1. A pixel comprising:
first to fourth driving transistors;
a first switching transistor including a first active pattern and electrically connected to the first driving transistor;
a second switching transistor including a second active pattern and electrically connected to the second driving transistor;
a first light emitting diode connected to the first driving transistor;
a second light emitting diode connected to the second driving transistor and spaced apart from the first light emitting diode in a first direction when viewed in a plan view;
a third light emitting diode connected to the third driving transistor and disposed between the first light emitting diode and the second light emitting diode when viewed in a plan view; and
a fourth light emitting diode connected to the fourth driving transistor and disposed between the first light emitting diode and the second light emitting diode when viewed in a plan view,
wherein a planar area of the first driving transistor is smaller than a planar area of each of the third driving transistor and the fourth driving transistor, a planar area of the second driving transistor is smaller than the planar area of the each of the third driving transistor and the fourth driving transistor, a first data signal is applied to the first driving transistor and the second driving transistor, a second data signal different from the first data signal is applied to the third driving transistor, and a third data signal different from the first data signal and the second data signal is applied to the fourth driving transistor, and
wherein the first switching transistor and the second switching transistor are connected to a same gate pattern to which a scan signal is applied.

2. The pixel of claim 1 , wherein the planar area of the first driving transistor is less than or equal to a half of the planar area of the each of the third driving transistor and the fourth driving transistor, and the planar area of the second driving transistor is less than or equal to a half of the planar area of the each of the third driving transistor and the fourth driving transistor.

3. The pixel of claim 1 , wherein a planar area of the first light emitting diode is smaller than a planar area of each of the third light emitting diode and the fourth light emitting diode, and a planar area of the second light emitting diode is smaller than the planar area of the each of the third light emitting diode and the fourth light emitting diode.

4. The pixel of claim 3 , wherein the planar area of the first light emitting diode is less than or equal to a half of the planar area of the each of the third light emitting diode and the fourth light emitting diode, and the planar area of the second light emitting diode is less than or equal to a half of the planar area of the each of the third light emitting diode and the fourth light emitting diode.

5. The pixel of claim 4 , further comprising:
a first capacitor connected to the first driving transistor;
a second capacitor connected to the second driving transistor;
a third capacitor connected to the third driving transistor; and
a fourth capacitor connected to the fourth driving transistor,
wherein a planar area of the first capacitor is less than or equal to a half of a planar area of each of the third capacitor and the fourth capacitor, and a planar area of the second capacitor is less than or equal to a half of the planar area of the each of the third capacitor and the fourth capacitor.

6. The pixel of claim 1 , further comprising:
a first capacitor connected to the first driving transistor;
a second capacitor connected to the second driving transistor;
a third capacitor connected to the third driving transistor; and
a fourth capacitor connected to the fourth driving transistor,
wherein a planar area of the first capacitor is less than or equal to a half of a planar area of each of the third capacitor and the fourth capacitor, and a planar area of the second capacitor is less than or equal to a half of the planar area of the each of the third capacitor and the fourth capacitor.

7. The pixel of claim 1 , wherein, when viewed in a planar view, the third light emitting diode and the fourth light emitting diode are spaced apart from each other in a second direction perpendicular to the first direction.

8. The pixel of claim 7 , wherein the first light emitting diode and the second light emitting diode partially overlap the third light emitting diode and the fourth light emitting diode in the first direction.

9. The pixel of claim 7 , wherein the first light emitting diode and the second light emitting diode partially overlap the third light emitting diode and the fourth light emitting diode in the second direction.

10. The pixel of claim 7 , wherein the first light emitting diode and the second light emitting diode partially overlap the third light emitting diode and the fourth light emitting diode in the first direction and the second direction.

11. A display device comprising:
a substrate;
first to fourth driving transistors;
a first switching transistor including a first active pattern and electrically connected to the first driving transistor;
a second switching transistor including a second active pattern and electrically connected to the second driving transistor;
a first light emitting diode connected to the first driving transistor;
a second light emitting diode connected to the second driving transistor and spaced apart from the first light emitting diode in a first direction when viewed in a plan view;
a third light emitting diode connected to the third driving transistor and disposed between the first light emitting diode and the second light emitting diode when viewed in a plan view;
a fourth light emitting diode connected to the fourth driving transistor and disposed between the first light emitting diode and the second light emitting diode when viewed in a plan view; and
an encapsulation layer disposed on the first to fourth light emitting diodes to cover the first to fourth light emitting diodes,
wherein a planar area of the first driving transistor is smaller than a planar area of each of the third driving transistor and the fourth driving transistor, a planar area of the second driving transistor is smaller than the planar area of the each of the third driving transistor and the fourth driving transistor, a first data signal is applied to the first driving transistor and the second driving transistor, a second data signal different from the first data signal is applied to the third driving transistor, and a third data signal different from the first data signal and the second data signal is applied to the fourth driving transistor, and
wherein the first switching transistor and the second switching transistor are connected to a same gate pattern to which a scan signal is applied.

12. The display device of claim 11 , wherein the planar area of the first driving transistor is less than or equal to a half of the planar area of the each of the third driving transistor and the fourth driving transistor, and the planar area of the second driving transistor is less than or equal to a half of the planar area of the each of the third driving transistor and the fourth driving transistor.

13. The display device of claim 11 , wherein a planar area of the first light emitting diode is smaller than a planar area of each of the third light emitting diode and the fourth light emitting diode, and a planar area of the second light emitting diode is smaller than the planar area of the each of the third light emitting diode and the fourth light emitting diode.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Sunkwang
• Jo Kangmoon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/8514

  characterised by their shape, e.g. plate or foil · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/853

  characterised by their shape · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title