Reduced display processing unit transfer time to compensate for delayed graphics processing unit render time

Patent metadata

Field	Value
Publication number	US-12249017-B2
Application number	US-202017794876-A
Country	US
Kind code	B2
Filing date	Feb 21, 2020
Priority date	Feb 21, 2020
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Devices and methods for reducing a DPU transfer time to compensate for a delayed GPU render time. After completion of rendering a second frame that follows a first frame, a frame processor determines whether the first frame is currently transferring to a display panel or has already been transferred to the display panel. At least one clock is used with a first set of clock speeds when the first frame is determined to be currently transferring and used with a second set of clock speeds when the first frame is determined to have already been transferred, the second set of clock speeds being faster than the first set of clock speeds. After completion of the transfer of the first frame, the second frame is transferred based on the set of clock speeds.

First claim

What is claimed is:

1. A method of frame processing, comprising:
determining whether a first frame is currently transferring or has been transferred after completion of a rendering of a second frame, the second frame following the first frame;
using, with at least one clock, a first set of clock speeds when the first frame is determined to be currently transferring and a second set of clock speeds when the first frame is determined to have been transferred, the second set of clock speeds being faster than the first set of clock speeds;
transferring the second frame based on the used set of clock speeds after completion of the transfer of the first frame;
extending a vertical synchronization (V SYNC ) period from a first period T to a second period T+a when the first frame has already been transferred, wherein the at least one clock is used with the second set of clock speeds; and
determining the second set of clock speeds based on reducing a transfer completion time of the second frame in order to provide a transfer of the second frame within a third period T−a.

2. The method of claim 1 , wherein the determining whether the first frame is currently transferring or has been transferred comprises determining whether a display processing unit (DPU) line counter indicates that the first frame is being transferred into a display buffer or has been fully transferred into the display buffer.

3. The method of claim 1 , wherein the at least one clock comprises at least one of a display serial interface (DSI) clock or a mobile display processor (MDP) clock.

4. The method of claim 1 , wherein the first set of clock speeds is a set of default clock speeds that provides for a transfer of a frame within a first period T.

5. The method of claim 1 , wherein the second set of clock speeds is based on a variable refresh rate of the second frame.

6. The method of claim 1 , further comprising switching from a command mode to a video mode when a constant display rate is requested.

7. An apparatus for frame processing, comprising:
a memory; and
at least one processor coupled to the memory and configured to:
determine whether a first frame is currently transferring or has been transferred after completion of a rendering of a second frame, the second frame following the first frame;
use, with at least one clock, a first set of clock speeds when the first frame is determined to be currently transferring and a second set of clock speeds when the first frame is determined to have been transferred, the second set of clock speeds being faster than the first set of clock speeds;
transfer the second frame based on the used set of clock speeds after completion of the transfer of the first frame
extend a vertical synchronization (V SYNC ) period from a first period T to a second period T+a when the first frame has already been transferred, wherein the at least one clock is used with the second set of clock speeds; and
determine the second set of clock speeds based on reducing a transfer completion time of the second frame in order to provide a transfer of the second frame within a third period T−a.

8. The apparatus of claim 7 , wherein for the determination of whether the first frame is currently transferring or has been transferred, the at least one processor is further configured to determine whether a display processing unit (DPU) line counter indicates that the first frame is being transferred into a display buffer or has been fully transferred into the display buffer.

9. The apparatus of claim 7 , wherein the at least one clock comprises at least one of a display serial interface (DSI) clock or a mobile display processor (MDP) clock.

10. The apparatus of claim 7 , wherein the first set of clock speeds is a set of default clock speeds that provides for a transfer of a frame within a first period T.

11. The apparatus of claim 7 , wherein the second set of clock speeds is based on a variable refresh rate of the second frame.

12. The apparatus of claim 7 , wherein the at least one processor is further configured to switch from a command mode to a video mode when a constant display rate is requested.

13. The apparatus of claim 7 , wherein the apparatus is a wireless communication device.

14. A non-transitory computer-readable medium storing computer executable code, the code when executed by a processor, causes the processor to:
determine whether a first frame is currently transferring or has been transferred after completion of a rendering of a second frame, the second frame following the first frame;
use, with at least one clock, a first set of clock speeds when the first frame is determined to be currently transferring and a second set of clock speeds when the first frame is determined to have been transferred, the second set of clock speeds being faster than the first set of clock speeds;
transfer the second frame based on the used set of clock speeds after completion of the transfer of the first frame extend a vertical synchronization (V SYNC ) period from a first period T to a second period T+a when the first frame has already been transferred, wherein the at least one clock is used with the second set of clock speeds; and
determine the second set of clock speeds based on reducing a transfer completion time of the second frame in order to provide a transfer of the second frame within a third period T−a.

15. The non-transitory computer-readable medium of claim 14 , wherein for the determination of whether the first frame is currently transferring or has been transferred, the processor is further configured to determine whether a display processing unit (DPU) line counter indicates that the first frame is being transferred into a display buffer or has been fully transferred into the display buffer.

16. The non-transitory computer-readable medium of claim 14 , wherein the first set of clock speeds is a set of default clock speeds that provides for a transfer of a frame within a first period T.

Assignees

• Qualcomm Inc

Inventors

• Xu Yongjun
• Zhang Nan
• Yao Wenkai
• Han Long

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G09G2360/18

  Use of a frame buffer in a display terminal, inclusive of the display panel · CPC title

• G09G2360/08

  Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title