Apparatus and method of controlling access to data stored in a non-trusted memory

Patent metadata

Field	Value
Publication number	US-12248409-B2
Application number	US-202017756877-A
Country	US
Kind code	B2
Filing date	Nov 12, 2020
Priority date	Dec 10, 2019
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

An apparatus including memory access circuitry for controlling access to data stored in the non-trusted memory, and memory security circuitry to verify integrity of data stored in the non-trusted memory. The memory security circuitry has authentication code generation circuitry for generating authentication codes to be associated with the data stored in the non-trusted memory, for use when verifying the integrity of the data. The apparatus also has a trusted storage, and the authentication code generation circuitry is arranged to generate different authentication codes, dependent on whether the authentication code is to be stored in the non-trusted memory or the trusted storage.

First claim

The invention claimed is:

1. An apparatus comprising:
memory access circuitry to control access to data stored in a non-trusted memory;
memory security circuitry to verify integrity of data stored in the non-trusted memory; and
a trusted storage;
the memory security circuitry having authentication code generation circuitry to generate authentication codes to be associated with the data stored in the non-trusted memory, for use when verifying the integrity of the data;
wherein the authentication code generation circuitry is arranged, for a given block of data for which an associated authentication code is to be generated:
to generate as the associated authentication code a first authentication code with a first size to be compared with a first comparison authentication code to verify the integrity of the given block of data when the associated authentication code is to be stored in the non-trusted memory, and
to generate as the associated authentication code a second authentication code with a second size less than the first size to be compared with a second comparison authentication code to verify the integrity of the given block of data when the associated authentication code is to be stored in the trusted storage.

2. The apparatus as claimed in claim 1 , wherein:
the apparatus resides within a domain of trust, and the non-trusted memory is outside of the domain of trust; and
the authentication code generation circuitry is arranged to generate the second authentication code in a manner that ensures that the second authentication code is not inferable from information residing outside of the domain of trust.

3. The apparatus as claimed in claim 1 , wherein:
the authentication code generation circuitry is arranged to employ an authentication code generation process that is dependent on which of the first authentication code and the second authentication code is being generated, so as to ensure that the second authentication code generated for the given block of data is not inferable from visibility of the first authentication code for that given block of data.

4. The apparatus as claimed in claim 3 , wherein the authentication code generation process is dependent on an input item of secret data, and the authentication code generation circuitry is arranged to cause a first item of secret data to be used when generating the first authentication code and a second item of secret data to be used when generating the second authentication code, wherein the second item of secret data is different to the first item of secret data.

5. The apparatus as claimed in claim 1 , wherein the authentication code generation circuitry is arranged to generate the second authentication code by applying an algorithm that uses as one input the given block of data.

6. The apparatus as claimed in claim 1 , wherein the authentication code generation circuitry is arranged to generate the second authentication code by applying an algorithm that uses as one input the first authentication code.

7. The apparatus as claimed in claim 1 , wherein the authentication code generation circuitry is arranged to generate the second authentication code by employing an algorithm that generates an intermediate authentication code that is of the first size, and then applying a further process to produce the second authentication code of the second size from the intermediate authentication code.

8. The apparatus as claimed in claim 7 , wherein the further process is a truncation process such that the second authentication code is a truncated version of the intermediate authentication code.

9. The apparatus as claimed in claim 1 , wherein the trusted storage is organised as a cache to store second authentication codes for a subset of the blocks of data stored in the non-trusted memory.

10. The apparatus as claimed in claim 9 , wherein the authentication code generation circuitry is arranged, when generating the second authentication code to be stored in the trusted storage, to also generate the first authentication code and store the generated first authentication code in the non-trusted memory, whereby on eviction of any second authentication code from the trusted storage, the corresponding first authentication code is present in the non-trusted memory.

11. The apparatus as claimed in claim 9 , wherein the authentication code generation circuitry is arranged, when generating the second authentication code to be stored in the trusted storage, to not store the first authentication code in the non-trusted memory, and on eviction of any second authentication code from the trusted storage, the authentication code generation circuitry is arranged to generate the corresponding first authentication code for storage in the non-trusted memory.

12. The apparatus as claimed in claim 9 , wherein:
the memory security circuitry is arranged, when reading a block of data from the non-trusted memory, to determine whether the associated authentication code is stored as a second authentication code in the trusted storage, and if so to verify the integrity of the read block of data using the second authentication code in the trusted storage.

13. The apparatus as claimed in claim 1 , wherein:
the memory security circuitry is arranged, when reading a block of data from the non-trusted memory, and on determining that the associated authentication code is not stored as a second authentication code in the trusted storage, to retrieve the first authentication code from the non-trusted memory and to employ the retrieved first authentication code when verifying the integrity of the read block of data.

14. The apparatus as claimed in claim 13 , wherein:
the memory security circuitry is arranged to employ the authentication code generation circuitry to:
apply a second code generation algorithm to generate from the retrieved first authentication code a reference second authentication code; and
generate a comparison second authentication code by first generating a comparison first authentication code from the read block of data, and then applying the second code generation algorithm using the comparison first authentication code in order to generate the comparison second authentication code;

wherein the memory security circuitry is arranged to verify the integrity of the read block of data by comparing the reference second authentication code to the comparison second authentication code.

15. The apparatus as claimed in claim 1 , wherein:
the authentication code generation circuitry is arranged to generate the second authentication code by applying an algorithm that uses as one input the first authentication code; and
the authentication circuitry is responsive to a first authentication code being retrieved from the non-trusted memory, to generate the corresponding second authentication code for storing in the trusted storage without reference to the associated block of data.

16. The apparatus as claimed in claim 1 , wherein:
the authentication code generation circuitry is arranged to apply a first process to generate the first authentication code and a second process to generate the second authentication code, the first and second processes sharing a common initial part.

17. The apparatus as claimed in claim 16 , wherein:
the common initial part comprises the performance of a hash function on the block of data using an input key to produce an intermediate value;
the authentication code generation circuitry is arranged to complete the first process by encrypting the intermediate value using first secret data in order to generate the firs

Assignees

• Advanced Risc Mach Ltd

Inventors

• Montaner Mas Hector
• Sandberg Andreas Lars
• Avanzi Roberto

Classifications

• G06F12/1441

  for a range · CPC title

• G06F12/0866

  for peripheral storage systems, e.g. disk cache · CPC title

• G06F12/1408 Primary

  by using cryptography (for digital transmission H04L9/00) · CPC title

• H04L9/3242

  involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title