Power governance of processing unit

Patent metadata

Field	Value
Publication number	US-12248351-B2
Application number	US-202318180462-A
Country	US
Kind code	B2
Filing date	Mar 8, 2023
Priority date	Dec 15, 2017
Publication date	Mar 11, 2025
Grant date	Mar 11, 2025

Abstract

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

First claim

The invention claimed is:

1. A processing platform comprising:
a plurality of processing units (PUs);
platform power governance circuitry to control an allocation of system power to the plurality of PUs;
measurement circuitry configured to:
measure a current utilization of one or more of the plurality of PUs at a current operating frequency using architectural performance counters, and
determine, based on the measured current utilization using architectural performance counters, a change in utilization or power of the one or more of the plurality of PUs; and

frequency control circuitry configured to:
determine, based on the identified change in utilization or power, a new target quantified power expenditure of the one or more of the plurality of PUs,
identify, based on the new target quantified power expenditure, a new operating frequency for the one or more of the plurality of PUs, and
update the current operating frequency of the one or more of the plurality of PUs to the new operating frequency,

wherein the measured current utilization of the one or more of the plurality of PUs at the current operating frequency using architectural performance counters is subject to a time window of performance requested by an operating system.

2. The processing platform of claim 1 , wherein the frequency control circuitry is further configured to update the current operating frequency of the one or more of the plurality of PUs to the new operating frequency based on a scaling factor.

3. A method for power management in a processing platform, comprising:
measuring a current utilization of one or more processing units (PUs) of a plurality of PUs at a current operating frequency using architectural performance counters;
identifying, based on the measured current utilization using the architectural performance counters, a change in utilization or power of the one or more of the plurality of PUs;
determining, based on the identified change in utilization or power, a new target quantified power expenditure of the one or more of the plurality of PUs;
identifying, based on the new target quantified power expenditure, a new operating frequency for the one or more of the plurality of PUs; and
updating the current operating frequency of the one or more of the plurality of PUs to the new operating frequency,
wherein the measuring the current utilization of the one or more of the plurality of PUs at the current operating frequency using architectural performance counters is subject to a time window of performance requested by an operating system.

4. The method of claim 3 , wherein the updating the current operating frequency of the one or more of the plurality of PUs to the new operating frequency is based on a scaling factor.

Assignees

• Tahoe Res Ltd

Inventors

• Cooper Barnes
• Seshadri Harinarayanan
• Muralidhar Rajeev
• Mubeen Noor

Classifications

• G06F1/3234 Primary

  Power saving characterised by the action undertaken · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/329

  by task scheduling · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/324

  by lowering clock frequency · CPC title