Image encoding apparatus, image encoding method, image decoding apparatus, image decoding method, program, and storage medium
US-2016366440-A1 · Dec 15, 2016 · US
Image processing device and image processing method
US12244835B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12244835-B2 |
| Application number | US-202017635384-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 18, 2020 |
| Priority date | Sep 20, 2019 |
| Publication date | Mar 4, 2025 |
| Grant date | Mar 4, 2025 |
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Abstract
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The present disclosure relates to an image processing device and an image processing method that enable image processing to be performed with a smaller number of line buffers.The image processing device includes a decoding unit that decodes a bitstream to generate an image according to an encoding standard in which a horizontal size of one tile is restricted for each level by a restriction value. The restriction value is set according to a maximum value MaxLumaPs of the number of luminance picture samples, and also restricts a vertical size of one tile. The present technology can be applied to, for example, an image processing system that performs encoding and decoding according to the VVC method.
First claim
Opening claim text (preview).
The invention claimed is: 1. An image processing device comprising: processing circuitry configured to decode a bitstream to generate an image according to an encoding standard in which a horizontal size of one tile is restricted by a restriction value, wherein the restriction value is enabled by a flag in the bitstream, wherein the restriction value is set according to each level that defines maximum resolution and frame rate and the following equation (1) using a maximum value MaxLumaPs of the number of luminance picture samples [ Math . 1 ] { Max_tile _width _in _luma _samples = MaxLumaPs × 2 = 0.5 × MaxLumaPs × 8 . ( 1 ) 2. The image processing device according to claim 1 , wherein the restriction value is set according to a maximum size of the image. 3. An image processing method comprising: allowing an image processing device to decode a bitstream to generate an image according to an encoding standard in which a horizontal size of one tile is restricted by a restriction value, wherein the restriction value is enabled by a flag in the bitstream, wherein the restriction value is set according to each level that defines maximum resolution and frame rate and the following equation (1) using a maximum value MaxLumaPs of the number of luminance picture samples { Max_tile _width _in _luma _samples = MaxLumaPs × 2 = 0.5 × MaxLumaPs × 8 . ( 1 ) 4. An image processing device comprising: processing circuitry configured to encode an image to generate a bitstream according to an encoding standard in which a horizontal size of one tile is restricted by a restriction value, wherein the restriction value is enabled by a flag in the bitstream, wherein the restriction value is set according to each level that defines maximum resolution and frame rate and the following equation (1) using a maximum value MaxLumaPs of the number of luminance picture samples { Max_tile _width _in _luma _samples = MaxLumaPs × 2 = 0.5 × MaxLumaPs × 8 . ( 1 )
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Classifications
using memory downsizing methods · CPC title
the region being a slice, e.g. a line of blocks or a group of blocks · CPC title
- H04N19/33Primary
in the spatial domain · CPC title
the region being a picture, frame or field · CPC title
Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks · CPC title
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- What does patent US12244835B2 cover?
- The present disclosure relates to an image processing device and an image processing method that enable image processing to be performed with a smaller number of line buffers.The image processing device includes a decoding unit that decodes a bitstream to generate an image according to an encoding standard in which a horizontal size of one tile is restricted for each level by a restriction valu…
- Who is the assignee on this patent?
- Sony Group Corp
- What technology area does this patent fall under?
- Primary CPC classification H04N19/33. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 04 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).