Semiconductor device

Patent metadata

Field	Value
Publication number	US-12244302-B2
Application number	US-202217670506-A
Country	US
Kind code	B2
Filing date	Feb 14, 2022
Priority date	Feb 16, 2021
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

A semiconductor device includes: a semiconductor base body including: a p-type substrate; and an n-type first semiconductor layer; a first electrode; a second electrode; an isolation film; an insulation film; and a third electrode disposed over the insulation film. The first electrode is electrically connected to a first circuit C 1 that is connected to a first power source Vin. The second electrode is electrically connected to a second circuit C 2 that is connected to a second power source Vcc. The semiconductor base body further includes a p-type back gate region that is formed in at least a region of the semiconductor base body that faces the third electrode by way of the insulation film with a depth that allows the back gate region to reach the substrate. A dopant concentration of the back gate region falls within a range of 1×10 10 cm −3 to 1×10 15 cm −3 .

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor base body including a substrate of a first conductivity type and a first semiconductor layer of a second conductivity type that is over the substrate;
a first electrode over the semiconductor base body, the first electrode contacting the semiconductor base body;
a second electrode over the semiconductor base body, the second electrode being spaced apart from the first electrode, the second electrode contacting the semiconductor base body;
an isolation film over a surface of the semiconductor base body in a region between the first electrode and the second electrode;
an insulation film over the surface of the semiconductor base body in a region between the second electrode and the isolation film; and
a third electrode over the insulation film, wherein the first electrode is configured to electrically connect to a first circuit and to a first power source,
the second electrode is configured to electrically connect to a second circuit and to a second power source, and
the semiconductor base body further includes
a back gate region of a conductivity type which is of the same conductivity type as that of the substrate, in at least a region of the semiconductor base body that faces the third electrode through the insulation film, and the back gate region at least in the region having a depth reaching the substrate, a dopant concentration of the back gate region falling within a range of 1×10 10 cm −3 to 1×10 15 cm −3 .

2. The semiconductor device according to claim 1 , wherein a second power source voltage that is an output voltage of the second power source is lower than a first power source voltage that is an output voltage of the first power source.

3. The semiconductor device according to claim 1 , wherein the third electrode is configured to electrically connect to the second electrode.

4. The semiconductor device according to claim 1 , wherein a predetermined voltage is applied to the third electrode in response to a signal.

5. The semiconductor device according to claim 1 , wherein the substrate is configured to connect to a reference potential.

6. The semiconductor device according to claim 1 , wherein
the first electrode is configured to electrically connect to a drive circuit configured to control turning on and off of a switch element of the first circuit and a capacitor connected to the drive circuit,
the second electrode is configured to electrically connect to a drive-use power source that is the second power source, and
the drive circuit is provided to the semiconductor base body.

7. The semiconductor device according to claim 1 , wherein
the semiconductor base body further includes a contact region of a second conductivity type having a higher dopant concentration than the first semiconductor layer, the contact region of the second conductivity type being in a region connected to the second electrode, and
the back gate region is also in a region between the contact region and the substrate.

8. The semiconductor device according to claim 1 , wherein the semiconductor base body further includes:
a contact region of a second conductivity type having a higher dopant concentration than the first semiconductor layer, the contact region of the second conductivity type being in a region connected to the second electrode; and
a semiconductor region of a second conductivity type having a lower dopant concentration than the contact region, the semiconductor region of the second conductivity type being in a region surrounding the contact region, and
the back gate region is also between the semiconductor region of the second conductivity type and the substrate.

9. The semiconductor device according to claim 1 , wherein the semiconductor base body further includes:
a contact region of a second conductivity type having a higher dopant concentration than the first semiconductor layer, the contact region of the second conductivity type being in a region connected to the second electrode; and
a semiconductor region of a second conductivity type having a lower dopant concentration than the contact region, the semiconductor region being in a region surrounding the contact region, and
the semiconductor region of the second conductivity type contacts with the substrate.

10. The semiconductor device according to claim 8 , wherein a dopant concentration of the semiconductor region of the second conductivity type is equal to a dopant concentration of the first semiconductor layer.

11. The semiconductor device according to claim 8 , wherein a dopant concentration of the semiconductor region of the second conductivity type is lower than a dopant concentration of the first semiconductor layer.

12. The semiconductor device according to claim 1 , further comprising
a fourth electrode over the semiconductor base body, the fourth electrode connecting to a reference potential, wherein
the back gate region in at least the region faces the second electrode, the third electrode and the fourth electrode, and the back gate region at least the region has the depth reaching to the substrate.

13. The semiconductor device according to claim 1 , wherein the back gate region directly contacts the substrate.

14. The semiconductor device according to claim 1 , wherein the back gate region is continuous with the substrate.

15. The semiconductor device according to claim 1 , wherein
the first semiconductor layer contacts the back gate region at a boundary which faces the third electrode.

Assignees

• Shindengen Electric Mfg

Inventors

• Kanda Ryo

Classifications

• H10D64/111

  Field plates · CPC title

• H10D62/235

  of IGFETs (IGFETs having buried channels H10D30/637) · CPC title

• H10D30/603 Primary

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H03K2017/515

  Mechanical switches; Electronic switches controlling mechanical switches, e.g. relais · CPC title

• H03K17/302

  in field-effect transistor switches · CPC title