ESD protection for multi-die integrated circuits (ICs) including integrated passive devices

Patent metadata

Field	Value
Publication number	US-12244137-B2
Application number	US-202217743637-A
Country	US
Kind code	B2
Filing date	May 13, 2022
Priority date	May 13, 2022
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

The described techniques address issues associated with electrostatic discharge (ESD) protection for multi-die integrated circuits (ICs). The techniques include the use of two or more semiconductor dies within a multi-die IC, which may include a first semiconductor die without ESD protection but with full ESD exposure. The first semiconductor receives ESD protection via a second semiconductor die that is integrated as part of the same package with the first semiconductor die. The second semiconductor die may be electrically more remote from ESD-exposed pins compared to the first semiconductor die. The first semiconductor die may include integrated passive devices. The second semiconductor die enables ESD protection for both semiconductor dies in the same integrated IC package.

First claim

What is claimed is:

1. A multi-die semiconductor integrated circuit (IC), comprising:
a first semiconductor die including a first set of pads and a second set of pads, the first set of pads being coupled to respective external pins of an IC package; and
a second semiconductor die including a third set of pads coupled to respective ones of the second set of pads,
wherein the first semiconductor die includes passive electrostatic discharge (ESD) protection circuitry configured to provide passive ESD protection for the first semiconductor die, the passive ESD circuitry comprising only passive ESD protection components, and
wherein the second semiconductor die includes active ESD protection circuitry configured to provide active ESD protection for the first semiconductor die in response to ESD events occurring via the external pins of the IC package to which the first set of pads are coupled.

2. The multi-die semiconductor IC of claim 1 , wherein the active ESD protection circuitry comprises clamp circuitry configured to provide the active ESD protection by performing voltage clamping in response to the ESD events to reduce a respective ESD-induced voltage at each of the first set of pads to less than a respective predetermined threshold voltage.

3. The multi-die semiconductor IC of claim 2 , wherein the passive ESD protection components comprise silicon integrated capacitors, and
wherein each one of a subset of the first set of pads is respectively coupled to a respective one of the silicon integrated capacitors, which is respectively coupled to a reference potential to provide the passive ESD protection for the first semiconductor die.

4. The multi-die semiconductor IC of claim 3 , wherein the predetermined threshold voltage represents, for each respective one of the silicon integrated capacitors of the first semiconductor die, a maximum voltage rating associated therewith.

5. The multi-die semiconductor IC of claim 3 , wherein the clamp circuitry is configured to shunt an ESD pulse current caused by the ESD events at voltages lower than a destructive limit of each respective one of the silicon integrated capacitors to which each respective one of the subset of the first set of pads in the first semiconductor die is respectively coupled.

6. The multi-die semiconductor IC of claim 1 , wherein the passive ESD protection components comprise silicon integrated capacitors, and
wherein each one of a subset of the first set of pads of the first semiconductor die is respectively coupled to a respective one of the silicon integrated capacitors, which is coupled to a respective reference potential to provide the passive ESD protection for the first semiconductor die.

7. The multi-die semiconductor IC of claim 1 , wherein the second semiconductor die further comprises a fourth set of pads, each pad from among the fourth set of pads being respectively coupled to one of the external pins of the IC package.

8. The multi-die semiconductor IC of claim 1 , wherein one of the third set of pads of the second semiconductor die is coupled to one of the first set of pads of the first semiconductor die via one of the external pins of the IC package.

9. The multi-die semiconductor IC of claim 1 , wherein the active ESD protection circuitry is configured to perform voltage clamping in response to the ESD events to reduce a respective ESD-induced voltage at each one of the first set of pads and each one of the third set of pads to less than a respective predetermined threshold voltage, thereby providing the active ESD protection for the first semiconductor die and the second semiconductor die.

10. The multi-die semiconductor IC of claim 1 , wherein each one of a first subset of the second set of pads is directly coupled to a respective one of the external pins of the IC package.

11. The multi-die semiconductor IC of claim 10 , wherein the passive ESD protection components comprise silicon integrated capacitors, and
wherein each one of the first subset of the second set of pads is coupled to a respective one of the silicon integrated capacitors that is coupled to a respective reference potential.

12. The multi-die semiconductor IC of claim 11 , wherein each one of a second subset of the second set of pads is indirectly coupled to a respective one of the external pins of the IC package via a respective one of the silicon integrated capacitors, which is coupled to a respective reference potential.

13. The multi-die semiconductor IC of claim 12 , wherein the respective reference potential to which each respective one of the silicon integrated capacitors of the first subset of the second set of pads is coupled is a same first reference potential, and
wherein the respective reference potential to which each respective one of the silicon integrated capacitors of the second subset of the second set of pads is coupled is a same second reference potential.

14. The multi-die semiconductor IC of claim 13 , wherein the first reference potential and the second reference potential is ground.

15. The multi-die semiconductor IC of claim 1 , wherein the passive ESD protection components comprise silicon integrated capacitors, and
wherein each one of a subset of the second set of pads is indirectly coupled to a respective one of the external pins of the IC package via a respective one of the silicon integrated capacitors, which is coupled to a respective reference potential.

16. The multi-die semiconductor IC of claim 1 , wherein the active ESD protection circuitry comprises active ESD protection circuitry components, with each respective one of the active ESD protection circuitry components being coupled between each respective one of the third set of pads and a reference potential.

17. The multi-die semiconductor IC of claim 16 , wherein one or more of the active ESD protection circuitry components comprise diodes.

18. The multi-die semiconductor IC of claim 16 , wherein one or more of the active ESD protection circuitry components comprise timer-based ESD protection circuitry.

19. The multi-die semiconductor IC of claim 1 , wherein the second semiconductor die is coupled to the first semiconductor die only via the third set of pads being coupled to respective ones of the second set of pads, which comprise internal connections of the IC package.

20. The multi-die semiconductor IC of claim 1 , wherein the second semiconductor die is not directly coupled to the external pins of the IC package.

Assignees

• Infineon Technologies Ag

Inventors

• Russ Christian Cornelius
• Esmark Kai

Classifications

• H10W90/755

  between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title