Display with replacement electrodes within pixel array for enhanced current spread
US-11139417-B1 · Oct 5, 2021 · US
US12243906B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12243906-B2 |
| Application number | US-202117525442-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 12, 2021 |
| Priority date | Nov 30, 2020 |
| Publication date | Mar 4, 2025 |
| Grant date | Mar 4, 2025 |
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A light source includes an epitaxial layer stack that includes an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer. The epitaxial layer stack includes a two-dimensional (2-D) array of mesa structures formed therein. The light source further includes an array of p-contacts electrically coupled to the p-type semiconductor layer of the 2-D array of mesa structures, a metal layer in regions surrounding individual mesa structures of the 2-D array of mesa structures, and a plurality of n-contacts coupling the metal layer to the n-type semiconductor layer at a plurality of locations between the individual mesa structures of the 2-D array of mesa structures.
Opening claim text (preview).
What is claimed is: 1. A light source comprising: an epitaxial layer stack including an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, the epitaxial layer stack including a two-dimensional (2-D) array of mesa structures formed therein; an array of p-contacts electrically coupled to the p-type semiconductor layer of the 2-D array of mesa structures; a metal layer surrounding each individual mesa structure of the 2-D array of mesa structures; and a plurality of n-contacts coupling the metal layer to the n-type semiconductor layer at a plurality of locations between the individual mesa structures of the 2-D array of mesa structures. 2. The light source of claim 1 , wherein the plurality of n-contacts and the array of p-contacts are on a same side of the n-type semiconductor layer or are on opposite sides of the n-type semiconductor layer. 3. The light source of claim 1 , further comprising an elongated n-contact at an area outside of the 2-D array of mesa structures, the elongated n-contact coupling the metal layer to the n-type semiconductor layer at the area outside of the 2-D array of mesa structures. 4. The light source of claim 1 , further comprising an array of micro-lenses on a surface of the n-type semiconductor layer. 5. The light source of claim 4 , wherein the array of micro-lenses is formed in the n-type semiconductor layer or a dielectric layer formed on the n-type semiconductor layer. 6. The light source of claim 4 , wherein the metal layer is between individual micro-lenses of the array of micro-lenses. 7. The light source of claim 1 , wherein the metal layer is on sidewalls of the 2-D array of mesa structures and regions between the 2-D array of mesa structures. 8. The light source of claim 7 , further comprising a dielectric layer between the sidewalls of the 2-D array of mesa structures and the metal layer, wherein the dielectric layer and the metal layer form a sidewall reflector. 9. The light source of claim 1 , further comprising a transparent conductive material layer between the array of p-contacts and the p-type semiconductor layer. 10. The light source of claim 1 , wherein each n-contact of the plurality of n-contacts is located at a center of a square region including four mesa structures. 11. The light source of claim 1 , wherein: a pitch of the 2-D array of mesa structures is equal to or less than 5 μm; and each mesa structure of the 2-D array of mesa structures is characterized by a lateral linear dimension equal to or less than 3 μm. 12. The light source of claim 1 , further comprising a second metal layer on a surface of the n-type semiconductor layer, wherein the metal layer and the second metal layer are on opposite sides of the n-type semiconductor layer. 13. The light source of claim 12 , wherein the second metal layer is configured to absorb visible light. 14. The light source of claim 1 , wherein the metal layer is characterized by at least one of: a thickness greater than 50 nm; or a drive current density equal to or greater than 1 A/cm 2 at a drive voltage equal to or less than 4.5 V. 15. The light source of claim 1 , wherein the metal layer includes Al, Au, Ni, Ti, Pd, Ge, Ag, Cu, or any combination thereof. 16. The light source of claim 1 , wherein at least one of the metal layer or the plurality of n-contacts is configured to absorb visible light. 17. The light source of claim 1 , wherein the n-type semiconductor layer includes a heavily doped sublayer. 18. The light source of claim 1 , further comprising a semiconductor substrate including electrical circuits fabricated thereon, the electrical circuits electrically coupled to the array of p-contacts and the plurality of n-contacts. 19. A method comprising: fabricating a micro-light emitting diode (micro-LED) array that comprises: an epitaxial layer stack including an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, the epitaxial layer stack including a two-dimensional (2-D) array of mesa structures formed therein; an array of p-contacts electrically coupled to the p-type semiconductor layer of the 2-D array of mesa structures; a metal layer surrounding each individual mesa structure of the 2-D array of mesa structures; and a plurality of n-contacts coupling the metal layer to the n-type semiconductor layer at a plurality of locations between the individual mesa structures of the 2-D array of mesa structures; fabricating electrical circuits on a semiconductor substrate; and bonding the micro-LED array to the semiconductor substrate such that the electrical circuits are coupled to the array of p-contacts and the plurality of n-contacts. 20. The method of claim 19 , further comprising forming a second metal layer on the n-type semiconductor layer, the metal layer and the second metal layer on opposite sides of the n-type semiconductor layer. 21. The method of claim 19 , wherein fabricating the micro-LED array comprises: growing the epitaxial layer stack on a second substrate; etching the epitaxial layer stack to form the 2-D array of mesa structures in the epitaxial layer stack; depositing a first dielectric layer on surfaces of the 2-D array of mesa structures; forming the plurality of n-contacts at regions between mesa structures of the 2-D array of mesa structures; depositing the metal layer on the first dielectric layer and the plurality of n-contacts; patterning the metal layer; forming a patterned second dielectric layer on the metal layer; forming the array of p-contacts in the patterned second dielectric layer; forming a patterned third dielectric layer; and forming p-electrodes and n-electrodes in the patterned third dielectric layer, the p-electrodes electrically connected to the array of p-contacts, and the n-electrodes electrically connected to the plurality of n-contacts.
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Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title
characterised by their shape, e.g. curved or truncated substrates · CPC title
Manufacture or treatment · CPC title
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