Electronic packages with integral heat spreaders

Patent metadata

Field	Value
Publication number	US-12243799-B2
Application number	US-202217738989-A
Country	US
Kind code	B2
Filing date	May 6, 2022
Priority date	Mar 24, 2021
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

An electronic device includes a substrate and a first gallium nitride (GaN) transistor formed on a first semiconductor die that is electrically coupled to the substrate. A second GaN transistor is formed on a second semiconductor die and is also electrically coupled to the substrate. An integral heat spreader is thermally coupled to the first and the second gallium nitride semiconductor dies and is electrically coupled to the substrate. A first bias voltage is applied to the first GaN transistor via the integral heat spreader and a second bias voltage is applied to the second GaN transistor via the integral heat spreader.

First claim

What is claimed is:

1. An electronic device comprising:
a substrate;
an electronic package attached to the substrate and comprising:
a leadframe;
a gallium nitride (GaN) based semiconductor die attached to the leadframe; and
a first molding material encapsulating at least a portion of the leadframe and at least a portion of the GaN-based semiconductor die;

an integral heat spreader thermally coupled to the leadframe; and
a second molding material encapsulating at least a portion of the substrate, at least a portion of the electronic package and at least a portion of the integral heat spreader.

2. The electronic device of claim 1 wherein the GaN-based semiconductor die is attached to the leadframe with an electrically conductive and thermally conductive die attach material.

3. The electronic device of claim 1 wherein the integral heat spreader includes a ceramic-containing layer sandwiched between a bottom metal layer and a top metal layer.

4. The electronic device of claim 1 wherein the electronic package is a first electronic package, the leadframe is a first leadframe and the GaN-based semiconductor die is a first GaN-based semiconductor die, the electronic device further comprising a second electronic package attached to the substrate and comprising:
a second leadframe; and
a second gallium nitride (GaN) based semiconductor die attached to the second leadframe.

5. The electronic device of claim 4 wherein the integral heat spreader includes a ceramic-containing layer sandwiched between a bottom metal layer and a top metal layer, the bottom metal layer including a first portion attached to the first leadframe and a second portion attached to the second leadframe, wherein the first portion is electrically isolated from the second portion.

6. The electronic device of claim 5 wherein the substrate is electrically coupled to the first portion and supplies a first bias voltage to the first semiconductor die, and wherein the substrate is electrically coupled to the second portion and supplies a second bias voltage to the second semiconductor die.

7. The electronic device of claim 4 wherein the first and the second GaN-based semiconductor dies form one phase of a half-bridge power converter circuit.

8. The electronic device of claim 1 wherein the electronic package includes a control integrated circuit die that includes a gate driver circuit coupled to the first GaN-based semiconductor die.

9. The electronic device of claim 1 wherein the GaN-based semiconductor die is attached to the leadframe with a plurality of wirebonds.

10. The electronic device of claim 1 wherein the electronic package is a dual-flat no-lead (DFN) configuration.

11. An electronic device comprising:
an electrical routing structure;
a formed metal layer;
a gallium nitride (GaN) based semiconductor die attached to the formed metal layer and electrically coupled to portions of the formed metal layer with wirebonds;

a first molding material encapsulating at least a portion of the formed metal layer and at least a portion of the GaN-based semiconductor die;
an integral heat spreader thermally coupled to the formed metal layer; and
a second molding material encapsulating at least a portion of the electrical routing structure, at least a portion of the formed metal layer and at least a portion of the integral heat spreader.

12. The electronic device of claim 11 , wherein the formed metal layer includes a die paddle and a plurality of terminals.

13. The electronic device of claim 12 wherein the GaN-based semiconductor die is attached to the die paddle and the wirebonds electrically couple the GaN-based semiconductor die to the plurality of terminals.

14. The electronic device of claim 12 wherein the formed metal layer, the GaN-based semiconductor die and the first molding compound form an electronic package.

15. The electronic device of claim 14 wherein the die paddle is at a top surface of the electronic package and the plurality of terminals are at a bottom surface of the electronic package.

16. The electronic device of claim 12 wherein the die paddle is attached to the integral heat spreader.

17. The electronic device of claim 12 wherein the die paddle is electrically coupled to the integral heat spreader.

18. The electronic device of claim 17 wherein the electrical routing structure is electrically coupled to the integral heat spreader and applies a bias voltage to the GaN-based semiconductor die via the die paddle.

19. A method of forming an electronic device, the method comprising:
coupling one or more GaN-based semiconductor die to a substrate;
encapsulating at least a portion of the substrate and at least a portion of the GaN-based semiconductor die in a first molding material;
attaching an integral heatsink to the one or more GaN-based semiconductor die and electrically coupling the integral heatsink to the substrate; and
encapsulating at least a portion of the integral heatsink in a second molding material.

20. The method of claim 19 further comprising applying an electrical bias to the one or more GaN-based semiconductor die via the integral heatsink.

Assignees

• Navitas Semiconductor Ltd

Inventors

• Bailley Charles
• Chu George
• Kinzer Daniel M

Classifications

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W40/037

  Assembling together parts thereof · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title