Controlling coarse pixel size from a stencil buffer

Patent metadata

Field	Value
Publication number	US-12243125-B2
Application number	US-202318517318-A
Country	US
Kind code	B2
Filing date	Nov 22, 2023
Priority date	Apr 10, 2017
Publication date	Mar 4, 2025
Grant date	Mar 4, 2025

Abstract

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

First claim

What is claimed is:

1. A system comprising:
a two-dimensional (2D) texture memory; and
logic to:
identify a stencil value that is associated with the 2D texture memory, and
determine a number of pixels that are to share an invocation of a pixel shader based on the stencil value, wherein the number of pixels is to be controlled via a stencil buffer.

2. The system of claim 1 , wherein the 2D texture memory includes the stencil buffer.

3. The system of claim 1 , wherein the logic is to limit an area of scene rendering based on the stencil value.

4. The system of claim 1 , wherein the stencil value includes ranges of bits that correspond to different dimensions of the pixels.

5. The system of claim 1 , wherein the stencil value is a single texel.

6. An apparatus comprising:
a substrate; and
logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the substrate to:
identify a stencil value that is associated with a 2D texture memory, and
determine a number of pixels that are to share an invocation of a pixel shader based on the stencil value, wherein the number of pixels is to be controlled via a stencil buffer.

7. The apparatus of claim 6 , wherein the 2D texture memory includes the stencil buffer.

8. The apparatus of claim 6 , wherein the logic coupled to the substrate is to limit an area of scene rendering based on the stencil value.

9. The apparatus of claim 6 , wherein the stencil value includes ranges of bits that correspond to different dimensions of the pixels.

10. The apparatus of claim 6 , wherein the stencil value is a single texel.

11. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
identify a stencil value that is associated with a 2D texture memory; and
determine a number of pixels that are to share an invocation of a pixel shader based on the stencil value, wherein the number of pixels is to be controlled via a stencil buffer.

12. The at least one non-transitory computer readable storage medium of claim 11 , wherein the 2D texture memory includes the stencil buffer.

13. The at least one non-transitory computer readable storage medium of claim 11 , wherein the instructions, when executed, cause the computing system to limit an area of scene rendering based on the stencil value.

14. The at least one non-transitory computer readable storage medium of claim 11 , wherein the stencil value includes ranges of bits that correspond to different dimensions of the pixels.

15. The at least one non-transitory computer readable storage medium of claim 11 , wherein the stencil value is a single texel.

16. A method comprising:
identifying a stencil value that is associated with a 2D texture memory; and
determining, with a graphics pipeline, a number of pixels that are to share an invocation of a pixel shader based on the stencil value, wherein the number of pixels is controlled via a stencil buffer.

17. The method of claim 16 , wherein the 2D texture memory includes the stencil buffer.

18. The method of claim 16 , the method includes limiting an area of scene rendering based on the stencil value.

19. The method of claim 16 , wherein the stencil value includes ranges of bits that correspond to different dimensions of the pixels.

20. The method of claim 16 , wherein the stencil value is a single texel.

Assignees

• Intel Corp

Inventors

• Vaidyanathan Karthik
• Surti Prasoonkumar
• Labbe Hugues
• Kuwahara Atsuo
• Kp Sameer
• Kennedy Jonathan
• Ramadoss Murali
• Apodaca Michael
• Venkatesh Abhishek

Classifications

• G06T11/10 Primary

  Texturing; Colouring; Generation of textures or colours (retouching, inpainting or scratch removal G06T5/77) · CPC title

• G06T2210/36

  Level of detail · CPC title

• G06T15/04

  Texture mapping · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T2210/52

  Parallel processing · CPC title