Semiconductor device and power amplifier

Patent metadata

Field	Value
Publication number	US-12237382-B2
Application number	US-202217827955-A
Country	US
Kind code	B2
Filing date	May 30, 2022
Priority date	Jun 18, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A semiconductor device includes: a substrate; a channel layer disposed on the substrate, wherein the channel layer is made of GaN; a barrier layer disposed on the channel layer, wherein the barrier layer is made of Al z Ga 1-z N; and an inserting structure inserted between the channel layer and the barrier layer. The inserting structure includes: a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of Al x Ga 1-x N; and a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of Al y Ga 1-y N, and y is greater than x. The semiconductor device further includes: a gate electrode disposed on the barrier layer; a source electrode and a drain electrode disposed on the barrier layer and respectively at opposite sides of the gate electrode; and a spike region formed below at least one of the source electrode and the drain electrode.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a channel layer disposed on the substrate, wherein the channel layer is made of gallium nitride;
a barrier layer disposed on the channel layer, wherein the barrier layer is made of Al z Ga 1-z N;
an inserting structure inserted between the channel layer and the barrier layer, comprising:
a first inserting layer disposed on the channel layer, wherein the first inserting layer is made of Al x Ga 1-x N; and
a second inserting layer disposed on the first inserting layer, wherein the second inserting layer is made of Al y Ga 1-y N, and y is greater than x;

a gate electrode disposed on the barrier layer;
a source electrode disposed on the barrier layer at a first side of the gate electrode; and
a drain electrode disposed on the barrier layer at a second side of the gate electrode opposite to the first side of the gate electrode, wherein a spike region is formed below at least one of the source electrode and the drain electrode.

2. The semiconductor device as claimed in claim 1 , wherein x satisfies 0.15≤x≤0.50.

3. The semiconductor device as claimed in claim 2 , wherein x is between 0.15 and 0.18.

4. The semiconductor device as claimed in claim 2 , wherein x is between 0.2 and 0.5.

5. The semiconductor device as claimed in claim 1 , wherein y satisfies 0.5<y≤1.

6. The semiconductor device as claimed in claim 5 , wherein y=1.

7. The semiconductor device as claimed in claim 1 , wherein z satisfies 0.18≤z≤0.50.

8. The semiconductor device as claimed in claim 1 , wherein a ratio of x to z is between 0.5 and 1.5.

9. The semiconductor device as claimed in claim 8 , wherein the ratio of x to z equals 1.

10. The semiconductor device as claimed in claim 1 , wherein the first inserting layer has a first thickness, the second inserting layer has a second thickness, and a ratio of the second thickness to the first thickness is between 0.25 and 3.

11. The semiconductor device as claimed in claim 10 , wherein the first thickness is between 5 Å and 20 Å.

12. The semiconductor device as claimed in claim 10 , wherein the second thickness is between 5 Å and 15 Å.

13. The semiconductor device as claimed in claim 1 , wherein the spike region further comprises:
a first spike region formed below the source electrode; and
a second spike region formed below the drain electrode.

14. The semiconductor device as claimed in claim 13 , wherein the first spike region and the second spike region extend into the channel layer through the barrier layer and the inserting structure.

15. The semiconductor device as claimed in claim 13 , wherein the first spike region and the second spike region comprises titanium (Ti).

16. The semiconductor device as claimed in claim 13 , wherein the first spike region and the second spike region comprise titanium nitride (TiN).

17. The semiconductor device as claimed in claim 1 , further comprising:
a buffer layer disposed between the substrate and the channel layer, wherein the buffer layer is made of Al w Ga 1-w N, and w satisfies 0≤w≤0.2.

18. The semiconductor device as claimed in claim 17 , wherein the spike region further extends into the buffer layer.

19. The semiconductor device as claimed in claim 1 , wherein at least one of the source electrode and the drain electrode comprises titanium (Ti), nickel (Ni), aluminum (Al), gold (Au), molybdenum (Mo), platinum (Pt), or a combination thereof.

20. A power amplifier, comprising the semiconductor device as claimed in claim 1 .

Assignees

• Win Semiconductors Corp

Inventors

• Huang Chieh-Chih
• Lin Yan-Cheng
• Lin Cheng-Kuo
• Wang Wei-Chou
• Lin Che-Kai
• Wu Jiun-De

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10P32/174

  being Group III-V material · CPC title

• H10P32/12

  between a solid phase and a gaseous phase · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title