Variable width for RF neighboring stacks

Patent metadata

Field	Value
Publication number	US-12237327-B2
Application number	US-202117523816-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Nov 10, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

Devices and methods to manufacture a stack of FET switches in presence of a neighboring stack of FET switches are described. The stack of FET switches is designed or manufactured so that at least its top FET has a width that is smaller than the width of its bottom FET. Other voltage handling configurations and distributions of widths are described.

First claim

The invention claimed is:

1. An integrated circuit (IC), comprising
a first stack comprising stacked FETs proceeding from a bottom FET of the first stack to a top FET of the first stack; the stacked FETs of the first stack being stacked on top of each other in a source to drain arrangement; and
a second stack comprising stacked FETs proceeding from a bottom FET of the second stack to a top FET of the second stack, the second stack neighboring the first stack, the stacked FETs of the second stack being stacked on top of each other in a source to drain arrangement,

wherein
each FET of the first stack or the second stack has a FET width extending in a top-to-bottom or bottom-to-top direction of the first stack or the second stack;
FET widths of upper FETs of the first stack are smaller than FET widths of lower FETs of the first stack, and
the FET widths of the upper FETs of the first stack and the FET widths of the lower FETs of the first stack are configured to have the upper FETs of the first stack having a positive capacitive compensation effect with the second stack and the lower FETs of the first stack having a negative capacitive compensation effect with the second stack.

2. The IC of claim 1 , wherein
the FET width of each FET of the upper FETs is smaller than the FET width of each FET of the lower FETs.

3. The IC of claim 2 , wherein
the first stack comprises i) a top third of stacked FETs including the upper FETs and ii) a bottom third of stacked FETs including the lower FETs, and
the FET width of each FET of the top third of stacked FETs is smaller than the FET width of each FET of the bottom third of stacked FETs.

4. The IC of claim 2 , wherein
the first stack comprises i) a top half of stacked FETs including the upper FETs and ii) a bottom half of stacked FETs including the lower FETs.

5. The IC of claim 4 , wherein
width distribution of FET widths in the top half of stacked FETs is a non-decreasing width distribution in a top-to-bottom direction along the first stack, wherein at least one of the FETs of the top half of stacked FETs has a width smaller than at least one lower FET of the FETs of the top half of stacked FETs.

6. The IC of claim 4 , wherein
the bottom half of stacked FETs includes i) a bottom half upper set of FETs and ii) a bottom half lower set of FETs and
FETs of the bottom half upper set have a non-decreasing width distribution in the top-to-bottom direction of the first stack, wherein at least one of the FETs of the bottom half upper set has a width smaller than at least one lower FET of the FETs of the bottom half upper set.

7. The IC of claim 6 , wherein
FETs of the bottom half lower set have a non-increasing width distribution in the top-to-bottom direction of the first stack, wherein at least one of the FETs of the bottom half lower set has a width larger than at least one lower FET of the FETs of the bottom half lower set.

8. An RF switch circuit comprising the IC of claim 1 , the first stack being a first switch stack and the second stack being a second switch stack.

9. An integrated circuit (IC), comprising
a first stack comprising stacked FETs proceeding from a bottom FET of the first stack to a top FET of the first stack; the stacked FETs of the first stack being stacked on top of each other in a source to drain arrangement, and
a second stack comprising stacked FETs proceeding from a bottom FET of the second stack to a top FET of the second stack, the second stack neighboring the first stack, the stacked FETs of the second stack being stacked on top of each other in a source to drain arrangement,

wherein
each FET of the first stack or the second stack has a FET width extending in a top-to-bottom or bottom-to-top direction of the first stack or the second stack;
FET widths of upper FETs of the first stack are smaller than a FET width of at least a first lower FET of the first stack, and
the FET widths of the upper FETs of the first stack and the FET widths of the at least the first lower FET of the first stack are configured to have the upper FETs of the first stack have a positive capacitive compensation effect with the second stack and lower FETs of the first stack have a negative capacitive compensation effect with the second stack.

10. The IC of claim 9 , wherein
the FET width of the at least first lower FET of the first stack is smaller than the FET width of at least a second lower FET of the first stack.

11. The IC of claim 9 , wherein
the FET width of the lower FET of the first stack is smaller than the FET width of at least a first upper FET of the first stack.

12. The IC of claim 11 , wherein
the FET width of the at least first upper FET of the first stack is smaller than the FET width of at least a second upper FET of the first stack.

13. An RF switch circuit comprising the IC of claim 11 , wherein the first stack constitutes a first switch stack and the second stack constitutes a second switch stack.

14. The IC of claim 9 , wherein
the first stack comprises i) a top half of stacked FETs including the upper FETs and ii) a bottom half of stacked FETs including the at least first lower FET.

15. The IC of claim 14 , wherein
width distribution of FET widths in the top half of stacked FETs is a non-decreasing width distribution in a top-to-bottom direction along the first stack, wherein at least one of the FETs of the top half of stacked FETs has a width smaller than at least one lower FET of the FETs of the top half of stacked FETs.

16. An RF switch circuit comprising the IC of claim 14 , wherein the first stack constitutes a first switch stack and the second stack constitutes a second switch stack.

17. An RF switch circuit comprising the IC of claim 9 , wherein the first stack constitutes a first switch stack and the second stack constitutes a second switch stack.

18. The IC of claim 9 , wherein
the first stack comprises i) a top third of stacked FETs including the upper FETs and ii) a bottom third of stacked FETs including the at least first lower FET, and
the FET width of each FET of the top third of stacked FETs is smaller than the FET width of each FET of the bottom third of stacked FETs.

Assignees

• Psemi Corp

Inventors

• Samal Shashi
• Allison Matt

Classifications

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• H10D88/01

  Manufacture or treatment · CPC title