Method for forming a buried metal line in a semiconductor substrate

Patent metadata

Field	Value
Publication number	US-12237207-B2
Application number	US-202318469374-A
Country	US
Kind code	B2
Filing date	Sep 18, 2023
Priority date	Jul 24, 2019
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

First claim

What is claimed is:

1. A method for forming a buried metal line in a semiconductor substrate, the method comprising:
conformally depositing a first liner over the semiconductor substrate;
depositing a spacer layer over the first liner;
forming, in the semiconductor substrate and at a level below a base of each semiconductor structure, a trench between a pair of semiconductor structures that protrude from the semiconductor substrate;
conformally depositing a second liner over the semiconductor substrate;
conformally depositing a barrier layer over the second liner;
selectively removing the barrier layer outside of the trench, wherein the barrier layer in the trench is disposed on the second liner;
selectively depositing a metal line material in the trench to thereby form a metal line in the trench, wherein the barrier layer is configured to promote deposition of the metal material in the trench, and wherein the second liner is configured to inhibit deposition of the metal material outside of the trench;
subsequent to selectively depositing the metal line material, conformally depositing a continuous capping liner over the metal line material and the pair of semiconductor structures; and
embedding the pair of semiconductor structures in an insulating layer.

2. The method according to claim 1 , wherein a height of the metal line exceeds a depth of the trench.

3. The method according to claim 1 , wherein the metal line corresponds to a buried power rail.

4. The method according to claim 1 , wherein the pair of semiconductor structures are formed by a pair of semiconductor fins.

5. The method according to claim 1 , wherein conformally depositing the continuous capping liner comprises depositing a Si 3 N 4 material.

6. The method according to claim 1 , further comprising:
subsequent to selectively depositing the metal line material, removing the spacer layer and a portion of the second liner outside of the trench, such that the first liner is disposed outside of the trench and the second liner is disposed within the trench.

7. The method according to claim 1 , wherein the spacer layer is conformally deposited over the first liner.

8. The method according to claim 1 , wherein the spacer layer is deposited over sidewall surfaces of the pair of semiconductor structures such that a gap is defined by the spacer layer between the pair of semiconductor structures.

Assignees

• Imec Vzw

Inventors

• Chan Boon Teik
• Tao Zheng
• Altamirano Sanchez Efrain
• Gupta Anshul
• Briggs Basoene

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/021 Primary

  of interconnections within wafers or substrates · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title