Pixel circuit and driving method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-12236871-B2
Application number	US-202218028743-A
Country	US
Kind code	B2
Filing date	May 19, 2022
Priority date	May 19, 2022
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A pixel circuit comprises a drive sub-circuit ( 101 ), writing sub-circuit ( 102 ), reset sub-circuit ( 103 ), voltage stabilizing sub-circuit ( 104 ), storage sub-circuit ( 105 ) and light emitting element. The drive sub-circuit is configured to provide a driving current to the light emitting element under control of signals of a first node (N 1 ) and a second node (N 2 ); the writing sub-circuit is configured to write a signal from a data signal terminal (Data) to N 2 under control of signal of a scan signal terminal (Gate); the storage sub-circuit is configured to store a voltage of N 1 ; the voltage stabilizing sub-circuit is configured to stabilize a voltage of an anode terminal of light emitting element through signal of a voltage stabilizing signal terminal (V 1 ); the reset sub-circuit is configured to reset anode terminal of light emitting element under control of signal of Gate and reset N 1 under control of signal of a reset control signal terminal (Reset).

First claim

The invention claimed is:

1. A pixel circuit, comprising a drive sub-circuit, a writing sub-circuit, a reset sub-circuit, a voltage stabilizing sub-circuit, a storage sub-circuit and a light emitting element, wherein
the drive sub-circuit is configured to provide a driving current to the light emitting element under control of signals of a first node and a second node;
the writing sub-circuit is configured to write a signal of a data signal terminal to the second node under control of a signal of a scan signal terminal;
the storage sub-circuit is configured to store a voltage of the first node;
the voltage stabilizing sub-circuit is configured to stabilize a voltage of an anode terminal of the light emitting element through a signal of a voltage stabilizing signal terminal; and
the reset sub-circuit is configured to reset the anode terminal of the light emitting element under control of the signal of the scan signal terminal and reset the first node under control of a signal of a reset control signal terminal;
the pixel circuit further comprises a compensation sub-circuit, a first light emitting control sub-circuit and a second light emitting control sub-circuit, wherein
the compensation sub-circuit is configured to compensate a threshold voltage of the drive sub-circuit under control of the signal of the scan signal terminal;
the first light emitting control sub-circuit is configured to form a conductive path between a first voltage terminal and the second node under control of a signal of a light emitting control signal terminal;
the second light emitting control sub-circuit is configured to form a conductive path between a third node and a fourth node under control of the signal of the light emitting control signal line; and
one terminal of the light emitting element is connected with the fourth node, and the other terminal of the light emitting element is connected with a second voltage terminal;
the voltage stabilizing sub-circuit comprises a second capacitor;
the drive sub-circuit comprises a third transistor;
the first light emitting control sub-circuit comprises a fifth transistor;
the second light emitting control sub-circuit comprises a six transistor;
in a light emitting stage, the signal of the light emitting control signal terminal is a low-level signal, and the signal of the scan signal terminal and the signal of the reset control signal terminal are both high-level signals; the signal of the light emitting control signal terminal is the low-level signal, so that the fifth transistor and the sixth transistor are turned on; a power supply voltage output by the first voltage terminal provides a drive voltage to a first electrode of the light emitting element through the turned-on fifth transistor, third transistor and sixth transistor, and the light emitting element emits light;
in the light emitting stage, while charging the fourth node, the second capacitor is charged; when the light emitting element stably emits light, two terminals of the second capacitor maintain a fixed potential difference, so that the fourth node is not be affected by crosstalk of adjacent transparent traces.

2. The pixel circuit according to claim 1 , wherein the storage sub-circuit comprises a first capacitor;
one terminal of the first capacitor is connected with the first node, and the other terminal of the first capacitor is connected with the first voltage terminal;
one terminal of the second capacitor is connected with the voltage stabilizing signal terminal, and the other terminal of the second capacitor is connected with the fourth node.

3. The pixel circuit according to claim 2 , wherein the voltage stabilizing signal terminal is any one of the following: a first voltage terminal, a second voltage terminal, and an initial signal terminal.

4. The driving circuit according to claim 2 , wherein the writing sub-circuit comprises a fourth transistor, wherein
a control electrode of the third transistor is connected with the first node, a first electrode of the third transistor is connected with the second node, and a second electrode of the third transistor is connected with the third node; and
a control electrode of the fourth transistor is connected with the scan signal terminal, a first electrode of the fourth transistor is connected with the data signal terminal, and a second electrode of the fourth transistor is connected with the second node.

5. The pixel circuit according to claim 4 , wherein the compensation sub-circuit comprises a second transistor, the reset sub-circuit comprises a first transistor and the seventh transistor;
a control electrode of the second transistor is connected with the scan signal terminal, a first electrode of the second transistor is connected with the third node, and a second electrode of the second transistor is connected with the first node;
a control electrode of the fifth transistor is connected with the light emitting control signal terminal, a first electrode of the fifth transistor is connected with the first voltage terminal, and a second electrode of the fifth transistor is connected with the second node;
a control electrode of the sixth transistor is connected with the light emitting control signal terminal, a first electrode of the sixth transistor is connected with the third node, and a second electrode of the sixth transistor is connected with the fourth node;
a control electrode of the first transistor is connected with the reset control signal terminal, a first electrode of the first transistor is connected with the first node, and a second electrode of the first transistor is connected with a first initial signal terminal; and
a control electrode of the seventh transistor is connected with the scan signal terminal, a first electrode of the seventh transistor is connected with a second initial signal terminal, and a second electrode of the seventh transistor is connected with the fourth node.

6. A display panel, comprising a plurality of sub-pixels, wherein at least one of the plurality of sub-pixels comprises the pixel circuit according to claim 1 .

7. The display panel according to claim 6 , wherein the display panel comprises a first display region and a second display region, the first display region at least partially surrounds the second display region;
the display panel comprises a plurality of first light emitting elements and a plurality of second light emitting elements; the display panel further comprises a plurality of first pixel circuits configured to drive first light emitting elements to emit light and a plurality of second pixel circuits configured to drive second light emitting elements to emit light;
a second pixel circuit is the pixel circuit, and the second pixel circuit comprises a first sub-part which is a part other than the voltage stabilizing sub-circuit and a second light emitting element;
the first light emitting elements, the first pixel circuits and first sub-parts of the second pixel circuits are located in the first display region, and first sub-parts of a plurality of second pixel circuits are distributed among a plurality of first pixel circuits; and
the voltage stabilizing sub-circuit and the second light emitting element are located in the second display region.

8. The display panel according to claim 6 , wherein on a plane perpendicular to the display panel, the display panel comprises a drive circuit layer provided on a base substrate, a light emitting structure layer provided on a side of the drive circuit layer away from the base substrate, and an encapsulation layer provided on a side of the light emitting structure layer away from the base substrate; the light emitting structure layer comprises an anode, a pixel definition layer, an organic light e

Assignees

• Mianyang Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Shen Yuan
• Xiong Lin
• Tu Jie
• Wang Zifeng
• Wang Danfeng
• Fan Jianmin
• Tang Qing

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title