Pixel circuit, driving method of pixel circuit, and display panel

US12236848B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12236848-B2
Application numberUS-202318240752-A
CountryUS
Kind codeB2
Filing dateAug 31, 2023
Priority dateSep 10, 2021
Publication dateFeb 25, 2025
Grant dateFeb 25, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit, a driving method of a pixel circuit, and a display panel. The pixel circuit includes an initialization module, a first storage module, a second storage module, a drive module, a data write module, a first light-emitting control module and a light-emitting module. The first light-emitting control module is connected between a first power supply and a first terminal of the drive module, the data write module is connected between a control terminal of the drive module and a data line, the light-emitting module is connected between a second terminal of the drive module and a second power supply, and the initialization module is configured to write an initialization voltage to the control terminal of the drive module and the light-emitting module in an initialization stage, and continuously write the initialization voltage to the control terminal of the drive module in a compensation stage.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising a drive module; a first storage module, wherein the first storage module is connected to a control terminal of the drive module and is configured to store a voltage of the control terminal of the drive module; a second storage module, wherein the second storage module is configured to store a voltage of a first terminal of the drive module or a voltage of a second terminal of the drive module; a data write module connected between the control terminal of the drive module and a data line and configured to transmit a data voltage provided by the data line to the control terminal of the drive module in a data write stage; a first light-emitting control module connected between a first power supply and a first terminal of the drive module and configured to transmit a voltage provided by the first power supply to the first terminal of the drive module after the first light-emitting control module is switched on; and a light-emitting module connected between a first power supply and a first terminal of the drive module and configured to transmit a voltage provided by the first power supply to the first terminal of the drive module after the first light-emitting control module is switched on; and an initialization module configured to: write an initialization voltage to the control terminal of the drive module and the light-emitting module in an initialization stage to initialize the control terminal of the drive module and the light-emitting module, and continuously write the initialization voltage to the control terminal of the drive module in a compensation stage while the data write module is in an off state. 2. The pixel circuit of claim 1 , wherein the initialization module further comprises: a first initialization module connected between the control terminal of the drive module and a first initialization signal line and configured to transmit a first initialization voltage provided by the first initialization signal line to the control terminal of the drive module after the first initialization module is switched on; and a second initialization module connected between a first terminal of the light-emitting module and a second initialization signal line, wherein a second terminal of the light-emitting module is connected to the second power supply, and the second initialization module is configured to transmit a second initialization voltage provided by the second initialization signal line to the first terminal of the light-emitting module after the second initialization module is switched on. 3. The pixel circuit of claim 2 , wherein a control terminal of the first initialization module is connected to a first scan line, a first terminal of the first initialization module is connected to the first initialization signal line, and a second terminal of the first initialization module is connected to the control terminal of the drive module; a control terminal of the data write module is connected to a second scan line, a first terminal of the data write module is connected to the data line, and a second terminal of the data write module is connected to the control terminal of the drive module; a control terminal of the second initialization module is connected to a third scan line or the first scan line, a first terminal of the second initialization module is connected to the second initialization signal line, and a second terminal of the second initialization module is connected to the first terminal of the light-emitting module; a control terminal of the first light-emitting control module is connected to a light-emitting control signal line, a first terminal of the first light-emitting control module is connected to the first power supply, a second terminal of the first light-emitting control module is connected to the first terminal of the drive module, and the second terminal of the drive module is connected to the first terminal of the light-emitting module. 4. The pixel circuit of claim 3 , wherein the drive module comprises a first transistor, the data write module comprises a second transistor, the first initialization module comprises a third transistor, the second initialization module comprises a fourth transistor, the first light-emitting control module comprises a fifth transistor, the first storage module comprises a first capacitor, the second storage module comprises a second capacitor, and the light-emitting module comprises a light-emitting diode; a gate of the third transistor is connected to the first scan line, a first pole of the third transistor is connected to the first initialization signal line, a second pole of the third transistor is connected to a gate of the first transistor, a first pole of the first transistor is connected to a second pole of the fifth transistor, a first pole of the fifth transistor is connected to the first power supply, a gate of the fifth transistor is connected to the light-emitting control signal line, a second pole of the first transistor is connected to a first pole of the light-emitting diode, and a second pole of the light-emitting diode is connected to the second power supply; a gate of the second transistor is connected to the second scan line, a first pole of the second transistor is connected to the data line, a second pole of the second transistor is connected to the gate of the first transistor, a gate of the fourth transistor is connected to the third scan line, a first pole of the fourth transistor is connected to the second initialization signal line, and a second pole of the fourth transistor is connected to the second pole of the first transistor; and a first terminal of the first capacitor is connected to the gate of the first transistor, a second terminal of the first capacitor is connected to the second pole of the first transistor, a first terminal of the second capacitor is connected to the first power supply, and a second terminal of the second capacitor is connected to the second pole of the first transistor. 5. The pixel circuit of claim 4 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are N-type transistors. 6. The pixel circuit of claim 4 , wherein the pixel circuit further comprises a second light-emitting control module comprising a sixth transistor, a gate of the sixth transistor is connected to the light-emitting control signal line, a first pole of the sixth transistor is connected to the second pole of the first transistor, a second pole of the sixth transistor is connected to the first pole of the light-emitting diode, and the second terminal of the first capacitor is connected to the second pole of the first transistor through the sixth transistor. 7. The pixel circuit of claim 3 , wherein the second initialization voltage is less than the first initialization voltage, and the first initialization voltage is less than a turn-on voltage of the light-emitting diode. 8. The pixel circuit of claim 3 , wherein in the initialization stage, the first light-emitting control module is configured to be switched off or switched on. 9. The pixel circuit of claim 3 , wherein the drive module comprises a first transistor, the data write module comprises a second transistor, the first initialization module comprises a third transistor, the second initialization module comprises a fourth transistor, the first light-emitting control module comprises a fifth transistor, the first storage module comprises a first capacitor, the second storage module comprises a second capacitor, and the light-emitting module comprises a light-emitting diode; a gate of the third transistor is connected to the first scan line, a first pole of the third t

Assignees

Inventors

Classifications

  • Details of power systems and of start or stop of display operation · CPC title

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

  • Layout of electrodes and connections · CPC title

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What does patent US12236848B2 cover?
A pixel circuit, a driving method of a pixel circuit, and a display panel. The pixel circuit includes an initialization module, a first storage module, a second storage module, a drive module, a data write module, a first light-emitting control module and a light-emitting module. The first light-emitting control module is connected between a first power supply and a first terminal of the drive …
Who is the assignee on this patent?
Kunshan Govisionox Optoelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 25 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).