Storage device, operating method of storage device, and electronic device

Patent metadata

Field	Value
Publication number	US-12236133-B2
Application number	US-202217575907-A
Country	US
Kind code	B2
Filing date	Jan 14, 2022
Priority date	Jul 1, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A storage device includes a nonvolatile memory device and a storage controller. The storage controller accesses the nonvolatile memory device based on a request of an external host device. The storage controller sends a signal to the external host device, based a throughput of accessing the nonvolatile memory device being within a specific range.

First claim

What is claimed is:

1. A storage device comprising:
a nonvolatile memory device including a plurality of memory cells; and
a storage controller configured to access the nonvolatile memory device based on an input/output (IO) request of an external host device to read data from or to write data to the nonvolatile memory device,
wherein the storage controller sends a redistribution request signal to the external host device, based on a throughput of accessing the nonvolatile memory device being within a specific range.

2. The storage device of claim 1 , wherein the redistribution request signal includes a local processor request that requests a local processor from the external host device, based on a non-uniform memory access (NUMA).

3. The storage device of claim 1 , wherein the storage controller sends a report signal including information of the throughput, based on the throughput of accessing the nonvolatile memory device not being within the specified range.

4. The storage device of claim 1 , wherein the redistribution request signal includes a message signaled interrupt (MSI) format defined in a peripheral component interconnect express (PCIe) standard.

5. The storage device of claim 1 , wherein the storage controller periodically sends a second signal including information of the throughput to the external host device.

6. The storage device of claim 1 , wherein the storage controller sends a second signal including information of the throughput to the external host device, based on a change in a range to which a value of the throughput belongs.

7. The storage device of claim 1 , wherein the storage controller sends a second signal to the external host device based on a value of the throughput being less than a threshold value, and
wherein the threshold value is less than a lower value of the specific range.

8. The storage device of claim 1 , wherein the specific range corresponds to a range from 60% to 70% of a maximum value of the throughput.

9. An operating method comprising:
accessing, at a storage controller, a nonvolatile memory device based on an input/output (IO) request of an external host device to read data from or to write data to the nonvolatile memory device;
monitoring, at the storage controller, a throughput of accessing the nonvolatile memory device; and
sending, from the storage controller, a redistribution request signal to the external host device based on the throughput being within a specific range.

10. The method of claim 9 , further comprising:
sending, from the storage controller to the external host device, a report signal including information of the throughput based on the throughput not being within the specified range.

11. The method of claim 9 , further comprising:
sending, from the storage controller to the external host device, a second signal including information of the throughput based on a change in a range to which a value of the throughput belongs.

12. The method of claim 9 , further comprising:
sending, from the storage controller to the external host device, a signal based on a value of the throughput being less than a threshold value.

13. An electronic device comprising:
a first processor group including a plurality of first processors;
a second processor group including a plurality of second processors, the second processor group being configured to communicate with the first processor group; and
a storage device connected with the second processor group,
wherein the plurality of second processors directly access the storage device,
wherein the plurality of first processors access the storage device through the plurality of second processors, and
wherein, based on a throughput of the storage device being within a specific range, the storage device sends a redistribution request signal to a processor that accesses the storage device from among the plurality of first processors and the plurality of second processors.

14. The electronic device of claim 13 , wherein, when an input and output (IO) requirement for the storage device necessary for a new process is less than a threshold value, the new process is executed by an idle processor that is in an idle state from among the plurality of first processors.

15. The electronic device of claim 13 , wherein, when an input and output (IO) requirement for the storage device necessary for a new process is greater than a threshold value, the new process is executed by an idle processor that is in an idle state from among the plurality of second processors.

16. The electronic device of claim 15 , wherein, when there is no idle processor that is in the idle state from among the plurality of second processors, the new process is executed by an idle processor that is in the idle state from among the plurality of first processors.

17. The electronic device of claim 13 , wherein, when a process executed by at least one first processor of the plurality of first processors accesses the storage device, based on the redistribution request signal the process is switched to be executed by at least one second processor that is in an idle state from among the plurality of second processors.

18. The electronic device of claim 13 , wherein, when a process executed by at least one second processor of the plurality of second processors accesses the storage device, the redistribution request signal is ignored.

19. The electronic device of claim 13 , wherein the redistribution request signal includes a message signaled interrupt (MSI) format defined in a peripheral component interconnect express (PCIe) standard.

20. The electronic device of claim 13 , wherein the plurality of first processors are implemented with multiple cores of a central processing unit, and the plurality of second processors are implemented with multiple cores of a central processing unit.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jaehwan
• Kim Jae Eun
• Kim Ji-Hoon
• Jun Walter
• Lee Jungwoo
• Lim Seung-Woo

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F3/0613

  in relation to throughput · CPC title

• G06F2213/0026

  PCI express · CPC title