Smart swapping and effective encoding of a double word in a memory sub-system

Patent metadata

Field	Value
Publication number	US-12236118-B2
Application number	US-202318541683-A
Country	US
Kind code	B2
Filing date	Dec 15, 2023
Priority date	Aug 6, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A processing device identifies a first set of bits associated with a translation unit of a memory device, wherein the first set of bits correspond to a page field; identifies a second set of bits associated with the translation unit, wherein the second set of bits corresponds to a block field; updates a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value; updates a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number; determines, based on the updated first portion and the updated second portion, that a swapping condition is satisfied; and performs a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
identifying a first set of bits associated with a translation unit of the memory device, wherein the first set of bits corresponds to a page field;
identifying a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field;
updating a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value;
updating a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number stored in the block field;
determining, based on the updated first portion and the updated second portion of the address mapping table, that a swapping condition is satisfied, wherein the swapping condition indicates that the page field and the block field are swapped; and
responsive to determining that the swapping condition is satisfied, performing a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

2. The system of claim 1 , further comprising:
storing a fixed value as a first bit of the second set of bits and a second bit of the second set of bits.

3. The system of claim 1 , wherein the translation unit comprises a plurality of fields, wherein the plurality of fields include the page field, the block field, a plane number field, and an offset field.

4. The system of claim 1 , wherein the processing device is to perform operations further comprising:
allocating the first set of bits according to a bit count.

5. The system of claim 1 , wherein the processing device is to perform operations further comprising:
responsive to determining that a value representing a page number stored in the page field does not satisfy a threshold criterion, storing the value representing the page number as a plurality of bits of the first set of bits.

6. The system of claim 1 , wherein the processing device is to perform operations further comprising:
responsive to determining that a value representing a page number stored in the page field does not satisfy a threshold criterion, storing the value representing the block number as a plurality of bits of the second set of bits.

7. The system of claim 1 , further comprising:
determining that a value representing a page number stored in the page field satisfies a threshold criterion; and
responsive to determining that the value representing the page number satisfies the threshold criterion, determining the difference between the value stored in the page field and the threshold value.

8. A method comprising:
identifying a first set of bits associated with a translation unit of a memory device, wherein the first set of bits corresponds to a page field;
identifying a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field;
updating a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value;
updating a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number stored in the block field;
determining, based on the updated first portion and the updated second portion of the address mapping table, that a swapping condition is satisfied, wherein the swapping condition indicates that the page field and the block field are swapped; and
responsive to determining that the swapping condition is satisfied, performing a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

9. The method of claim 8 , further comprising:
storing a fixed value as a first bit of the second set of bits and a second bit of the second set of bits.

10. The method of claim 8 , wherein the translation unit comprises a plurality of fields, wherein the plurality of fields include the page field, the block field, a plane number field, and an offset field.

11. The method of claim 8 , further comprising:
allocating the first set of bits according to a bit count.

12. The method of claim 8 , further comprising:
responsive to determining that a value representing a page number stored in the page field does not satisfy a threshold criterion, storing the value representing the page number as a plurality of bits of the first set of bits.

13. The method of claim 8 , further comprising:
responsive to determining that a value representing a page number stored in the page field does not satisfy a threshold criterion, storing the value representing the block number as a plurality of bits of the second set of bits.

14. The method of claim 8 , further comprising:
determining that a value representing a page number stored in the page field satisfies a threshold criterion; and
responsive to determining that the value representing the page number satisfies the threshold criterion, determining the difference between the value stored in the page field and the threshold value.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
identifying a first set of bits associated with a translation unit of a memory device, wherein the first set of bits corresponds to a page field;
identifying a second set of bits associated with the translation unit of the memory device, wherein the second set of bits corresponds to a block field;
updating a first portion of an address mapping table corresponding to the second set of bits with a value representing a difference between a value stored in the page field and a threshold value;
updating a second portion of the address mapping table corresponding to the first set of bits with a value representing a block number stored in the block field;
determining, based on the updated first portion and the updated second portion of the address mapping table, that a swapping condition is satisfied, wherein the swapping condition indicates that the page field and the block field are swapped; and
responsive to determining that the swapping condition is satisfied, performing a data access operation on a set of memory cells residing at a location corresponding to the translation unit.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the translation unit comprises a plurality of fields, wherein the plurality of fields include the page field, the block field, a plane number field, and an offset field.

17. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:
responsive to determining that a value representing a page number stored in the page field does not satisfy a threshold criterion, storing the value representing the page number as a plurality of bits of the first set of bits.

18. The non-transitory computer-readable storage medium of claim 15 , wherein the processing device is to perform operations further comprising:
responsive to determining that a value representing a page number stored in the page field does not satisfy a threshold criterion, storing the value representing the block number as a plurality of bits of t

Assignees

• Micron Technology Inc

Inventors

• Wei Meng

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title