Maintenance operations in a DRAM

Patent metadata

Field	Value
Publication number	US-12236111-B2
Application number	US-202418610888-A
Country	US
Kind code	B2
Filing date	Mar 20, 2024
Priority date	Jan 22, 2009
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.

First claim

What is claimed is:

1. A memory controller to control a dynamic random access memory device (DRAM) that includes a data interface, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
command logic to generate a refresh command, wherein the refresh command includes a plurality of bits that specify that the DRAM perform an internal refresh operation to refresh data stored in at least one bank of the plurality of memory banks; and
a command interface to transmit the refresh command to the DRAM, wherein the refresh command includes an operation code to enable calibration of the data interface of the DRAM in parallel with the internal refresh operation.

2. The memory controller of claim 1 , wherein the operation code to enable calibration of the data interface of the DRAM in parallel with the internal refresh operation includes a bit to specify a calibration of odd or even links of the data interface of the DRAM.

3. The memory controller of claim 1 , wherein the refresh command specifies an auto-refresh operation.

4. The memory controller of claim 1 , wherein the operation code to enable calibration of the data interface of the DRAM includes a bit to specify a transmit or receive calibration of the data interface.

5. The memory controller of claim 1 , wherein the operation code to enable calibration of the data interface of the DRAM includes one or more bits to specify an equalization calibration of the data interface.

6. The memory controller of claim 1 , further comprising a timer to detect a condition to trigger the command logic to generate the refresh command.

7. The memory controller of claim 1 , further comprising a receiver to receive a data pattern from the DRAM in connection with the calibration of the data interface.

8. A method of operation of a memory controller to control a dynamic random access memory device (DRAM) that includes a data interface, and a plurality of memory cells, the method comprising:
generating a refresh command, wherein the refresh command includes a plurality of bits that specify that the DRAM perform an internal refresh operation during an interval; and
transmitting the refresh command to the DRAM, wherein the refresh command includes an operation code to enable calibration of the data interface of the DRAM during the interval.

9. The method of claim 8 , wherein the operation code further includes one or more bits to specify a calibration of odd or even links of the data interface of the DRAM.

10. The method of claim 8 , wherein the refresh command specifies an auto-refresh operation.

11. The method of claim 8 , wherein the operation code further includes one or more bits that specifies a transmit or receive calibration of the data interface.

12. The method of claim 8 , wherein the operation code further includes one or more bits to specify an equalization calibration of the data interface.

13. The method of claim 8 , further comprising
detecting a condition to trigger a command logic circuit to generate the refresh command.

14. The method of claim 8 , further comprising
receiving a data pattern from the DRAM in connection with calibration of the data interface.

15. A memory controller to control a dynamic random access memory device (DRAM) that includes a data interface, and a plurality of memory banks, each bank including a plurality of rows of memory cells, the memory controller comprising:
a command interface to transmit a refresh command to the DRAM, wherein the refresh command includes:
(i) a plurality of bits that specify that the DRAM perform an internal refresh operation to refresh data; and
(ii) an operation code to enable a calibration operation of the data interface of the DRAM; and
a receiver to receive a data pattern from the DRAM in connection with the calibration operation of the data interface.

16. The memory controller of claim 15 , wherein the operation code to enable a calibration operation of the data interface of the DRAM further includes one or more bits to specify a calibration of odd or even links of the data interface of the DRAM.

17. The memory controller of claim 15 , wherein the refresh command specifies an auto-refresh operation.

18. The memory controller of claim 15 , wherein the operation code to enable a calibration operation of the data interface of the DRAM further includes one or more bits to specify a transmit or receive calibration of the data interface.

19. The memory controller of claim 15 , wherein the operation code to enable a calibration operation of the data interface of the DRAM further includes one or more bits to specify an equalization calibration of the data interface.

20. The memory controller of claim 15 , further comprising: command logic circuitry to generate the refresh command; and a timer to detect a condition to trigger the command logic circuitry to generate the refresh command.

Assignees

• Rambus Inc

Inventors

• Ware Frederick A
• Palmer Robert E
• Poulton John W

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G11C11/40615

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G06Q20/00

  Payment architectures, schemes or protocols (apparatus for performing or posting payment transactions G07F7/08, G07F19/00; electronic cash registers G07G1/12) · CPC title