Displaying base plate and manufacturing method thereof, and displaying device

Patent metadata

Field	Value
Publication number	US-12235557-B2
Application number	US-202117765769-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Jun 29, 2021
Publication date	Feb 25, 2025
Grant date	Feb 25, 2025

Abstract

A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

First claim

The invention claimed is:

1. A displaying base plate, wherein the displaying base plate comprises:
a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer comprises a first electrode pattern;
a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and
a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed close to the substrate, an orthographic projection of the second electrode layer on the substrate covers an orthographic projection of the through hole on the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer, and the second planarization layer fills the through hole to planarize the through hole;
an active area and a non-active area, and the active area comprises an opening region and a non-opening region, wherein the non-opening region at least refers to a region where an orthographic projection of a barrier layer on the substrate overlaps with the substrate, the opening region refers to a region where the orthographic projection of the barrier layer on the substrate does not overlap with the substrate;
a first thin-film transistor disposed on one side of the substrate that is closer to the first electrode layer, the first thin-film transistor is located at the active area, the first thin-film transistor comprises a first active layer, a first grid insulating layer, a first grid, a first interlayer dielectric layer and a first source that are disposed in stack, the first active layer is disposed close to the substrate, and the first active layer comprises a drain contacting region, and the drain contacting region is located at the opening region;
orthographic projections of the first grid insulating layer and the first interlayer dielectric layer on the substrate do not intersect or overlap with the opening region;
the drain contacting region is the first electrode pattern; and
the drain contacting region is directly contacted with the substrate.

2. The displaying base plate according to claim 1 , wherein the active area further comprises a data line and a scanning line, the first source extends in a first direction to form the data line, the first grid extends in a second direction intersecting with the first direction to form the scanning line, and both of orthographic projections of the data line and the scanning line on the substrate cover an orthographic projection of a channel region of the first active layer on the substrate.

3. The displaying base plate according to claim 1 , wherein the barrier layer and a second interlayer dielectric layer are disposed in stack between the first active layer and the substrate, the barrier layer is disposed closer to the substrate, and an orthographic projection of the barrier layer on the substrate covers an orthographic projection of a channel region of the first active layer on the substrate.

4. The displaying base plate according to claim 3 , wherein the active area further comprises a data line and a scanning line, and the orthographic projection of the barrier layer on the substrate covers orthographic projections of the data line and the scanning line on the substrate.

5. The displaying base plate according to claim 3 , wherein the barrier layer is connected to a constant-electric-potential input terminal.

6. The displaying base plate according to claim 3 , wherein the barrier layer and the first source are connected by via holes disposed in the second interlayer dielectric layer, the first grid insulating layer and the first interlayer dielectric layer.

7. The displaying base plate according to claim 1 , wherein the displaying base plate further comprises a second thin-film transistor, the second thin-film transistor is located at the non-active area, and a material of an active layer of the second thin-film transistor comprises a polycrystalline silicon.

8. The displaying base plate according to claim 1 , wherein a channel region of the first active layer comprises a first channel region, a first resistor region and a second channel region that are disposed sequentially in a first direction, the first grid comprises a first sub-grid and a second sub-grid that are disposed, respectively, an orthographic projection of the first sub-grid on the substrate covers an orthographic projection of the first channel region on the substrate, and an orthographic projection of the second sub-grid on the substrate covers an orthographic projection of the second channel region on the substrate.

9. A displaying device, wherein the displaying device comprises the displaying base plate according to claim 1 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zhang Zhen
• Li Fuqiang
• Zhang Zhenyu
• Di Yunping
• Wang Lizhong
• Fang Zheng
• Han Jiahui
• Wang Yawei
• Zhang Chenyang
• Xu Chengfu
• Ning ce
• Liang Pengxia
• Zhou Feihu
• Meng Xianqin
• Peng Weiting
• Wang Qiuli
• Tong Binbin
• Huang Rui
• Zhou Tianmin
• Yang Wei

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/021

  of multiple TFTs · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title