Metastability-free clockless single flux quantum logic circuitry

Patent metadata

Field	Value
Publication number	US-12231123-B2
Application number	US-202217971700-A
Country	US
Kind code	B2
Filing date	Oct 24, 2022
Priority date	Oct 24, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

First claim

What is claimed is:

1. A device, comprising:
a logic circuit comprising a clockless single flux quantum logic gate, wherein the clockless single flux quantum logic gate comprises:
a plurality of input ports, and an output port;
a plurality of dynamic storage loop circuits;
an output Josephson junction coupled to an output of each of the dynamic storage loop circuits and configured to drive the output port;
a plurality of isolation buffer circuits, wherein each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit;
wherein each isolation buffer circuit comprises a Josephson junction that is configured to absorb a circulating current of an antifluxon without switching, which is injected into the respective dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port, to prevent the antifluxon from being output from the respective input port; and
wherein each isolation buffer circuit is configured to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon that is present in the respective dynamic storage loop circuit.

2. The device of claim 1 , wherein the output Josephson junction is biased at a level which enables the output Josephson junction to switch in response to a circulating current of a fluxon that is injected into at least one of the dynamic storage loop circuits to generate the single flux quantum output pulse on the output port.

3. The device of claim 1 , wherein the output Josephson junction is biased at a level which enables the output Josephson junction to switch in response to circulating currents of fluxons injected in each of at least two dynamic storage loop circuits to generate the single flux quantum output pulse on the output port.

4. The device of claim 1 , wherein the isolation buffer circuits have a same circuit architecture, and each of the isolation buffer circuits comprises a multi-stage Josephson transmission line buffer circuit.

5. The device of claim 4 , wherein each multi-stage Josephson transmission line buffer circuit comprises a two-stage Josephson transmission line buffer circuit.

6. The device of claim 4 , wherein each multi-stage Josephson transmission line buffer circuit comprises an output stage which is coupled to an input of the respective dynamic storage loop circuit, wherein the output stage comprises the Josephson junction that is configured to absorb the circulating current of the antifluxon without switching, wherein the Josephson junction is biased at a level which allows the Josephson junction of the output stage to absorb the circulating current of the antifluxon, which flows out from the input of the respective dynamic storage loop circuit, without switching the Josephson junction of the output stage as a result of a combination of a backpropagating antifluxon current and a static bias current which biases the Josephson junction of the output stage.

7. The device of claim 6 , wherein the Josephson junction of the output stage is biased at a level in which a magnitude of the static bias current is in a range of about 20 percent to about 40 percent of a critical current of the Josephson junction of the output stage.

8. The device of claim 1 , wherein the dynamic storage loop circuits have a same circuit architecture, wherein the dynamic storage loop circuits each comprise:
a series combination of a superconducting inductor and a dynamic switch circuit, coupled to an input port and to the output port;
wherein the dynamic switch circuit comprises a parallel combination of a first Josephson junction, and a series combination of a second Josephson junction and a resistor; and
wherein the dynamic switch circuit is configured to enable dynamic self-resetting of an internal state of the dynamic storage loop circuit based on a first time constant for temporarily storing magnetic flux of a fluxon or antifluxon, and a second time constant for ejecting the stored magnetic flux.

9. The device of claim 1 , wherein the clockless single flux quantum logic gate comprises a clockless logic OR gate comprising at least two input ports.

10. The device of claim 1 , wherein the clockless single flux quantum logic gate comprises a clockless logic majority gate comprising at least three input ports.

11. A device, comprising:
a logic circuit comprising a clockless single flux quantum logic gate, wherein the clockless single flux quantum logic gate comprises:
a first input port, a second input port, and an output port;
a first dynamic storage loop circuit;
a second dynamic storage loop circuit;
an output Josephson junction which is coupled to an output of the first dynamic storage loop circuit and an output of the second dynamic storage loop circuit, and which is configured to drive the output port;
a first multi-stage Josephson transmission line buffer circuit coupled between the first input port and the first dynamic storage loop circuit, wherein the first multi-stage Josephson transmission line buffer circuit comprises an output stage which comprises a Josephson junction that is configured to absorb a circulating current of an antifluxon without switching, which is injected into the first dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port, in order to prevent the antifluxon from being output from the first input port, and configured to switch and inject a fluxon into the first dynamic storage loop circuit in response to a single flux quantum pulse applied to the first input port, and annihilate an antifluxon that is present in the first dynamic storage loop circuit; and
a second multi-stage Josephson transmission line buffer circuit coupled between the second input port and the second dynamic storage loop circuit, wherein the second multi-stage Josephson transmission line buffer circuit comprises an output stage which comprises a Josephson junction that is configured to absorb a circulating current of an antifluxon without switching, which is injected into the second dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port, in order to prevent the antifluxon from being output from the second input port, and configured to switch and inject a fluxon into the second dynamic storage loop circuit in response to a single flux quantum pulse applied to the second input port, and annihilate an antifluxon that is present in the second dynamic storage loop circuit.

12. The device of claim 11 , wherein the output Josephson junction is biased at a level in which a magnitude of a static bias current is at least 60 percent of a critical current of the output Josephson junction.

13. The device of claim 11 , wherein the first multi-stage Josephson transmission line buffer circuit and the second multi-stage Josephson transmission line buffer circuit each comprise a two-stage Josephson transmission line buffer circuit comprising a respective input stage and the output stage.

14. The device of claim 11 , wherein the Josephson junctions of the output stages of the first multi-stage Josephson transmission line buffer circuit and the second multi-stage Josephson transmission line buffer circuit are each biased with a respective static bias current having a magnitude that is in a range of about 20 percent to about 40 percent of a critical current of the Josephson junction of the outpu

Assignees

• IBM

Inventors

• Rylov Sergey
• Bulzacchelli John Francis
• Beck Matthew

Classifications

• H03K19/1954 Primary

  with injection of the control current · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title