Transistor device having a cell field and method of fabricating a gate of the transistor device

Patent metadata

Field	Value
Publication number	US-12230706-B2
Application number	US-202318102831-A
Country	US
Kind code	B2
Filing date	Jan 30, 2023
Priority date	Feb 6, 2020
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

In an embodiment, a transistor device a semiconductor substrate having a main surface, and a cell field including a plurality of transistor cells of a power transistor. The cell field further includes: a body region of a second conductivity type; a source region of a first conductivity type on or in the body region, the first conductivity type opposing the second conductivity type; a gate trench in the main surface of the semiconductor substrate; a gate dielectric lining the gate trench; a metal gate electrode arranged in the gate trench on the gate dielectric; and an electrically insulating cap arranged on the metal gate electrode. A method of fabricating a gate of the transistor device is also described.

First claim

What is claimed is:

1. A method of fabricating a gate of a transistor device that comprises a semiconductor substrate having a main surface, and a cell field comprising a plurality of transistor cells of a power transistor, the method comprising:
forming a gate trench in the main surface of the semiconductor substrate in the cell field;
forming a gate dielectric layer over the main surface of the semiconductor substrate and within the gate trench;
forming a metal gate electrode on the gate dielectric layer over the main surface of the semiconductor substrate and within the gate trench;
removing the metal gate electrode from the main surface of the semiconductor and partially over the gate trench such that a remainder of the metal gate electrode within the gate trench comprises an upper surface that is substantially coplanar with an upper surface of the gate dielectric layer formed over the main surface;
removing an upper portion of the remainder of the metal gate electrode from the gate trench such that an upper surface of the metal gate electrode is recessed within the gate trench;
forming an insulating layer on the recessed upper surface of the metal gate electrode and over the main surface of the semiconductor substrate; and
removing the insulating layer and the gate dielectric layer over the main surface and partially over the gate trench such that a remainder of the insulating layer forms an electrically insulating cap that comprises an upper surface that is substantially coplanar with the main surface of the semiconductor substrate,
before forming the gate dielectric layer, forming a dielectric layer at least on a bottom of the gate trench and over the main surface of the semiconductor substrate; and
when removing the insulating layer and the gate dielectric layer from the main surface, also removing the dielectric layer from the main surface.

2. The method of claim 1 , further comprising:
after removing the insulating layer and the gate dielectric layer from the main surface, forming a second insulating layer that extends over the main surface of the semiconductor substrate and over the upper surface of the electrically insulating cap.

3. The method of claim 1 , further comprising:
forming at least one charge compensation structure within the semiconductor substrate, wherein the at least one charge compensation structure comprises a columnar field plate in a columnar field plate trench that extends into the main surface and is positioned laterally adjacent the gate trench.

4. The method of claim 1 , wherein forming the metal gate electrode comprises:
forming a liner layer on the gate dielectric layer over the main surface of the semiconductor substrate and within the gate trench; and
depositing a filler material on the liner layer over the main surface of the semiconductor substrate and within the gate trench.

5. The method of claim 4 , wherein the liner layer comprises titanium nitride, and wherein the filler material comprises tungsten.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Neumann Ingmar
• Hutzler Michael
• Laforet David
• Moennich Roland
• Siemieniec Thomas Ralf

Classifications

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/665

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671) · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D64/514

  characterised by the insulating layers · CPC title