Semiconductor devices having highly integrated sheet and wire patterns therein

Patent metadata

Field	Value
Publication number	US-12230630-B2
Application number	US-202217571954-A
Country	US
Kind code	B2
Filing date	Jan 10, 2022
Priority date	Jun 11, 2021
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate having first and second regions therein;
a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate;
a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction orthogonal to the first direction;
a plurality of semiconductor sheet patterns, which are spaced apart from each other in a third direction orthogonal to the first and second directions to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern;
a first gate insulating film which separates the plurality of semiconductor sheet patterns from the first gate electrode;
a second lower semiconductor pattern, which protrudes from the semiconductor substrate in the second region and extends in the first direction across the semiconductor substrate;
a plurality of wire patterns spaced apart from each other in the third direction, on the second lower semiconductor pattern; and
a second gate insulating film wrapped around each of the plurality of wire patterns;
wherein a thickness of the first gate insulating film less than a thickness of the second gate insulating film; and
wherein an average thickness of the plurality of sheet patterns, as measured in the third direction, is greater than average thickness of the plurality of wire patterns, as measured in the third direction.

2. The semiconductor device of claim 1 , further comprising:
a field insulating film extending on opposing sides of the second lower semiconductor pattern;
wherein the second lower semiconductor pattern includes a first portion which overlaps the field insulating film in the second direction, and a second portion extending on the first portion; and
wherein a slope of a side wall of the second portion of the second lower semiconductor pattern is unequal to a slope of a side wall of the first portion of the second lower semiconductor pattern.

3. The semiconductor device of claim 1 , wherein a width of an upper surface of the first lower semiconductor pattern in the second direction is greater than a width of the second lower semiconductor pattern in the second direction.

4. The semiconductor device of claim 1 , wherein an upper surface of the first lower semiconductor pattern is coplanar with an upper surface of the second lower semiconductor pattern.

5. The semiconductor device of claim 1 , wherein a number of the plurality of sheet patterns is greater than a number of the plurality of wire patterns.

6. The semiconductor device of claim 1 , wherein the first gate insulating film includes a first interface film, and a first high dielectric constant film on the first interface film,
wherein the second gate insulating film includes a second interface film, and a second high dielectric constant film on the second interface film, and
wherein the first interface film is thinner than the second interface film.

7. The semiconductor device of claim 6 , wherein the first high dielectric constant film and the second high dielectric constant film have the same thickness.

8. The semiconductor device of claim 1 ,
wherein the plurality of semiconductor sheet patterns includes a first sheet pattern and a second sheet pattern; and wherein the first sheet pattern is located between the second sheet pattern and the first lower semiconductor pattern; and
wherein a width of the first sheet pattern is greater than a width of the second sheet pattern, as measured in the second direction.

9. The semiconductor device of claim 1 ,
wherein the plurality of wire patterns includes a first wire pattern and a second wire pattern, which is located between the second wire pattern and the second lower semiconductor pattern; and
wherein a cross-sectional area of the first wire pattern is greater than a cross-sectional area of the second wire pattern.

10. A semiconductor device comprising:
a first lower semiconductor pattern, which protrudes from a first region of a substrate and extends lengthwise in a first direction across the substrate;
a first gate electrode, which extends across the first lower semiconductor pattern and the substrate in a second direction orthogonal to the first direction;
a plurality of semiconductor sheet patterns, which are spaced apart from each other in a third direction orthogonal to the first and second directions to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern;
a first gate insulating film which separates the plurality of semiconductor sheet patterns from the first gate electrode, said first gate insulating film including a first interface film, and a first high dielectric constant film on the first interface film;
a second lower semiconductor pattern, which protrudes from a second region of a substrate and extends lengthwise in the first direction across the substrate;
a second gate electrode, which extends across the second lower semiconductor pattern and the substrate in the second direction;
a plurality of wire patterns spaced apart from each other in the third direction, on the second lower semiconductor pattern; and
a second gate insulating film wrapped around each of the plurality of wire patterns, said second gate insulating film including a second interface film, and a second high dielectric constant film on the second interface film;
wherein the second interface film is thicker than the first interface film.

11. The semiconductor device of claim 10 , wherein a thickness of the first high dielectric constant film is equal to a thickness of the second high dielectric constant film.

12. The semiconductor device of claim 10 , further comprising:
a field insulating film extending on both sides of the second lower semiconductor pattern;
wherein the second lower semiconductor pattern includes a first portion which overlaps the field insulating film in the second direction, and a second portion extending on the first portion; and
wherein a slope of a side wall of the second portion of the second lower semiconductor pattern is unequal to a slope of a side wall of the first portion of the second lower semiconductor pattern.

13. The semiconductor device of claim 10 , wherein the plurality of wire patterns includes a first wire pattern and a second wire pattern; wherein the first wire pattern extends between the second lower semiconductor pattern and the second wire pattern; and wherein cross-sectional area of the first wire pattern is greater than a cross-sectional area of the second wire pattern.

14. The semiconductor device of claim 10 , wherein a width of an upper surface of the first lower semiconductor pattern is greater than a width of an upper surface of the second lower semiconductor pattern, as measured in the second direction.

15. A semiconductor device, comprising:
a first lower semiconductor pattern, which protrudes from a first region of a substrate and extends lengthwise in a first direction across the substrate;
a first gate electrode, which crosses the first lower semiconductor pattern in a second direction, which is orthogonal to the first direction;
first to third sheet patterns, which are vertically stacked on the first lower semiconductor pattern, and spaced apart from the first lower semiconductor pattern in a third direction orthogonal to the first direction and the second direction;
a first gate insulating film, which surrounds the first to third sheet patte

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Kyung In
• Choi Do Young
• Kim Dong Myoung
• Kim Jin Bum
• Yu Hae Jun

Classifications

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/0128 Primary

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title