Scan circuit, display substrate, and display apparatus

Patent metadata

Field	Value
Publication number	US-12230216-B2
Application number	US-202218245534-A
Country	US
Kind code	B2
Filing date	May 31, 2022
Priority date	May 31, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive a start signal or an output signal from a previous scan unit, a first processing subcircuit, a second processing subcircuit, and an output subcircuit. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node. The first node is coupled to a gate electrode of the first output transistor. The first processing subcircuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

First claim

What is claimed is:

1. A scan circuit, comprising a plurality of stages, wherein a respective stage of the scan circuit comprises a respective scan unit configured to provide a control signal to at least a row of subpixels;
wherein the respective scan unit comprises an input subcircuit configured to receive from an input terminal a start signal or an output signal from a previous scan unit of a previous stage, a first processing subcircuit, a second processing subcircuit, and an output subcircuit configured to output an output signal from an output terminal;
wherein the output subcircuit comprises a first output transistor;
wherein the input subcircuit comprises a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node; and
the first node is coupled to a gate electrode of the first output transistor;
wherein the first processing subcircuit comprises a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal; and
the first reference terminal is configured to receive a first reference signal;
wherein the first processing subcircuit further comprises a first control transistor coupled between a second node and the first reference terminal;
a gate electrode of the first control transistor is coupled to the input terminal, and is configured to receive the start signal or the output signal from the previous scan unit of the previous stage;
a source electrode of the first control transistor is coupled to the first reference terminal, and is configured to receive the first reference signal; and
a drain electrode of the first control transistor is coupled to the second node, which is coupled to gate electrodes of the first switch transistor and the second switch transistor.

2. The scan circuit of claim 1 , wherein gate electrodes of the first input transistor and the second input transistor are coupled to a first terminal, and are configured to receive a first clock signal from the first terminal; and
a source electrode of the first output transistor is coupled to a second terminal, and is configured to receive a second clock signal from the second terminal.

3. The scan circuit of claim 1 , wherein the second processing subcircuit comprises a second control transistor coupled between a second node and a second reference terminal;
the second reference terminal is configured to receive a second reference signal; and
a gate electrode of the second control transistor is coupled to a third terminal, and is configured to receive a third clock signal from the third terminal.

4. The scan circuit of claim 1 , wherein the first processing subcircuit further comprises a third control transistor coupled between a third node and a second reference terminal;
a gate electrode of the third control transistor is coupled to the first node;
a source electrode of the third control transistor is coupled to the second reference terminal, and is configured to receive a second reference signal from the second reference terminal; and
a drain electrode of the third control transistor is coupled to a drain electrode of the first switch transistor and a source electrode of the second switch transistor.

5. The scan circuit of claim 1 , wherein the input subcircuit further comprises a fourth control transistor coupled between a fourth node and a second terminal;
the second terminal is configured to receive a second clock signal;
the fourth node is coupled to a drain electrode of the first input transistor and a source electrode of the second input transistor; and
a gate electrode of the fourth control transistor is coupled to the output terminal, and is configured to receive the output signal from the output terminal.

6. The scan circuit of claim 1 , wherein the output subcircuit further comprises a second output transistor coupled between the first reference terminal and the output terminal; and
a gate electrode of the second output transistor is coupled to gate electrodes of the first switch transistor and the second switch transistor.

7. A display substrate, comprising:
a scan circuit;
wherein the scan circuit comprises a plurality of stages, wherein a respective stage of the scan circuit comprises a respective scan unit configured to provide a control signal to at least a row of subpixels;
wherein the respective scan unit comprises an input subcircuit configured to receive from an input terminal a start signal or an output signal from a previous scan unit of a previous stage, a first processing subcircuit, a second processing subcircuit, and an output subcircuit configured to output an output signal from an output terminal;
wherein the output subcircuit comprises a first output transistor;
wherein the input subcircuit comprises a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node; and
the first node is coupled to a gate electrode of the first output transistor;
wherein the first processing subcircuit comprises a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal; and
the first reference terminal is configured to receive a first reference signal;
wherein the first output transistor and a second output transistor of the output subcircuit are arranged in a first region;
input transistors, switch transistors, and control transistors of the respective scan unit are arranged in a second region; and
capacitors of the respective scan unit are arranged in a third region;
wherein the display substrate further comprises one or more clock signal lines arranged in a fourth region;
wherein the fourth region, the second region, the first region, and the third region are sequentially arranged.

8. The display substrate of claim 7 , wherein, in the second region, the first input transistor and the second input transistor are on a side of the first switch transistor and the second switch transistor closer to one or more clock signal lines; and
the first switch transistor and the second switch transistor are on a side of the first input transistor and the second input transistor closer to the first output transistor and the second output transistor.

9. The display substrate of claim 7 , comprising a semiconductor material layer;
wherein the semiconductor material layer comprises active layers of one or more transistors of the respective scan unit;
an active layer of the first input transistor and an active layer of the second input transistor are parts of a first unitary structure in the semiconductor material layer; and
at least a portion of the first unitary structure has a L shape or an I shape.

10. The display substrate of claim 9 , wherein the first unitary structure further comprises an active layer of a fourth control transistor.

11. The display substrate of claim 7 , comprising a semiconductor material layer;
wherein the semiconductor material layer comprises active layers of one or more transistors of the respective scan unit;
an active layer of the first switch transistor and an active layer of the second switch transistor are parts of a second unitary structure in the semiconductor material layer; and
at least a portion of the second unitary structure has a L shape or an I shape.

12. The display substrate of claim 11 , wherein the second unitary structure further includes an active layer of a first control transistor.

13. The display substrate of claim 7 , wherein the first output transistor has a first occupied area;
the second output transistor has a second occupied area;
the first occupied

Assignees

• Boe Technology Group Co Ltd

Inventors

• Lu Jiangnan
• Shan Zhenzhen
• Zhu Jianchao
• Shang Guangliang
• Yao Xing

Classifications

• G09G2310/08

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• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title