Display substrate and method of driving the same, display panel and display device

Patent metadata

Field	Value
Publication number	US-12230210-B2
Application number	US-202218547182-A
Country	US
Kind code	B2
Filing date	Sep 30, 2022
Priority date	Sep 30, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A display substrate, including: a plurality of partition control signal lines disposed on a base substrate; and a plurality of sub-pixels disposed on the base substrate, at least one of the sub-pixels includes a pixel circuit and a light emitting device. The pixel circuit includes a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor. The first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one partition control signal line. The first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase, and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase.

First claim

What is claimed is:

1. A display substrate, the display substrate comprising a display region and a non-display region, wherein the display substrate comprises:
a base substrate;
a plurality of data signal lines, a plurality of first scanning signal lines, a plurality of partition control signal lines, a plurality of first initialization signal lines and a plurality of second scanning signal lines disposed on the base substrate; and
a plurality of sub-pixels disposed on the base substrate and located in the display region, wherein the plurality of sub-pixels are arranged in an array in a first direction and a second direction in the display region, the first direction intersects the second direction, and at least one of the plurality of sub-pixels comprises a pixel circuit and a light emitting device,
wherein the pixel circuit comprises a switch transistor, a first partition control transistor, a drive transistor and a first initialization transistor;
wherein the switch transistor is electrically connected to at least one of the plurality of first scanning signal lines and at least one of the plurality of data signal lines, the first initialization transistor is electrically connected to at least one of the plurality of first initialization signal lines and at least one of the plurality of second scanning signal lines, the drive transistor is electrically connected to the light emitting device, and the first partition control transistor is electrically connected to the switch transistor, the first initialization transistor, the drive transistor and at least one of the plurality of partition control signal lines;
wherein the switch transistor is configured to: transmit a data signal on the data signal line to the first partition control transistor in response to a first scanning signal on the first scanning signal line; the first initialization transistor is configured to: transmit a first initialization signal on the first initialization signal line to the first partition control transistor in response to a second scanning signal on the second scanning signal line; the first partition control transistor is configured to: in response to a partition control signal on the partition control signal line, selectively transmit a received first initialization signal to a gate electrode of the drive transistor in an initialization phase and selectively transmit a received data signal to the gate electrode of the drive transistor in a data writing phase; and the drive transistor is configured to: provide a drive signal to the light emitting device in response to a voltage difference between the gate electrode of the drive transistor and a first electrode of the drive transistor; and
wherein in one and same pixel circuit, in the second direction, an orthographic projection of the first partition control transistor on the base substrate is located between an orthographic projection of the first initialization transistor on the base substrate and an orthographic projection of the drive transistor on the base substrate.

2. The display substrate according to claim 1 , wherein in one and same pixel circuit, an orthographic projection of the first partition control transistor on the base substrate and an orthographic projection of the switch transistor on the base substrate are arranged in the first direction.

3. The display substrate according to claim 1 , wherein the display substrate further comprises a plurality of light emitting control signal lines and a plurality of first power lines disposed on the base substrate;
wherein the pixel circuit further comprises a light emitting control transistor electrically connected to the drive transistor, at least one of the plurality of light emitting control signal lines and at least one of the plurality of first power lines;
wherein the light emitting control transistor is configured to: transmit a first voltage signal on the first power line to the first electrode of the drive transistor in response to a light emitting control signal on the light emitting control signal line; and
wherein in one and same pixel circuit, an orthographic projection of the light emitting control transistor on the base substrate is located on a side of an orthographic projection of the drive transistor on the base substrate away from an orthographic projection of the first partition control transistor on the base substrate.

4. The display substrate according to claim 1 , wherein the display substrate further comprises a plurality of second partition control transistors, a plurality of third scanning signal lines and a plurality of second initialization signal lines disposed on the base substrate, and at least one of the plurality of second partition control transistors is electrically connected to at least one of the plurality of partition control signal lines, at least one of the plurality of second initialization signal lines and pixel circuits in the plurality of sub-pixels; and
wherein the at least one of the second partition control transistors is configured to: selectively transmit a second initialization signal on the second initialization signal line to the pixel circuit electrically connected to the second partition control transistor, in response to a partition control signal on the partition control signal line.

5. The display substrate according to claim 4 , wherein the pixel circuit further comprises a second initialization transistor, the pixel circuit is electrically connected to the second partition control transistor through the second initialization transistor, and the second initialization transistor is further electrically connected to the drive transistor and at least one of the plurality of third scanning signal lines; and
wherein the second initialization transistor is configured to: transmit a received second initialization signal to the first electrode of the drive transistor in response to a third scanning signal on the third scanning signal line.

6. The display substrate according to claim 5 , wherein in one and same pixel circuit, an orthographic projection of the second initialization transistor on the base substrate is located on a side of an orthographic projection of the drive transistor on the base substrate away from an orthographic projection of the first partition control transistor on the base substrate.

7. The display substrate according to claim 5 , wherein an orthographic projection of the at least one of the second partition control transistors on the base substrate and an orthographic projection of the second initialization transistor of the pixel circuit electrically connected to the at least one of the second partition control transistors are arranged in the first direction.

8. The display substrate according to claim 4 , wherein an orthographic projection of the at least one of the second partition control transistors on the base substrate at least partially overlaps with an orthographic projection of the partition control signal line electrically connected to the at least one of the second partition control transistors on the base substrate.

9. The display substrate according to claim 4 , wherein for the at least one of the second partition control transistors and the pixel circuit electrically connected to the at least one of the second partition control transistors, the second partition control transistor and the first partition control transistor in the pixel circuit are electrically connected to one and same partition control signal line.

10. The display substrate according to claim 4 , wherein a plurality of pixel circuits electrically connected to the at least one of the second partition control transistors are arranged in the first direction and disposed adjacent

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd
• Heifei Boe Joint Tech Co Ltd

Inventors

• Wu Liu
• Yuan Can
• Yuan Zhidong
• Xu Cheng
• Ding Luke
• Li Yongqian
• Liu Xiuting

Classifications

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/04

  Partial updating of the display screen · CPC title

• G09G2310/0221

  with use of split matrices (G09G3/3644 and G09G3/3666 take precedence) · CPC title