Block data load with transpose into memory

Patent metadata

Field	Value
Publication number	US-12229570-B2
Application number	US-202217952270-A
Country	US
Kind code	B2
Filing date	Sep 25, 2022
Priority date	Sep 25, 2022
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

Block data load with transpose techniques are described. In one example, an input is received, at a control unit, specifying an instruction to load a block of data to at least one memory module using a transpose operation. Responsive to the receiving the input by the control unit, the block of data is caused to be loaded to the at least one memory module by transposing the block of data to form a transposed block of data and storing the transposed block of data in the at least one memory.

First claim

What is claimed is:

1. A method comprising:
responsive to receiving, by a control circuit of a processor, a single transpose and load instruction specifying a plurality of blocks of data to be processed in a transposed form by a processor array of the processor, fetching, by the control circuit of the processor, the data for processing by storing the transposed form of the data in at least one memory module circuit of the processor array without generating an intermediate representation of the transposed form of the data; and
processing, by the processor array, the transposed form of the data stored in the at least one memory module circuit.

2. The method of claim 1 , wherein:
the processor is part of a single instruction multiple data (SIMD) processor unit that includes the processor array and the at least one memory module circuit of the processor array.

3. The method of claim 1 , wherein the plurality of blocks of data includes a first matrix that is column major and the transposed form of the data includes a second matrix that is row major.

4. The method of claim 1 , wherein the plurality of blocks of data includes a first matrix that is row major and the transposed form of the data includes a second matrix that is column major.

5. A processor comprising:
a control circuit configured to:
receive a single transpose and load instruction specifying a plurality of blocks of data to be maintained in at least one memory module circuit in a transposed form that is suitable for processing; and
responsive to receiving the single transpose and load instruction, fetch the data by storing the transposed form of the data in the at least one memory module circuit without maintaining an intermediate representation of the transposed form of the data; and

a processor array configured to process the transposed form of the data.

6. The processor of claim 5 , wherein the processor array includes the at least one memory module circuit.

7. The processor of claim 6 , wherein the processor array includes at least one processor element corresponding to the at least one memory module circuit.

8. The processor of claim 5 , wherein the plurality of blocks of data includes a first matrix that is column major and the transposed form of the data includes a second matrix that is row major.

9. The processor of claim 5 , wherein the plurality of blocks of data includes a first matrix that is row major and the transposed form of the data includes a second matrix that is column major.

10. The processor of claim 5 , wherein the plurality of blocks of data includes training data for training a machine-learning model.

11. The processor of claim 10 , wherein the processor array is further configured to train the machine-learning model based on the transposed form of the data.

12. The processor of claim 11 , wherein the processor array is further configured to:
process subsequent data using the trained machine-learning model; and
output a result of processing the subsequent data.

13. The processor of claim 12 , wherein, in being configured to process the subsequent data, the processor array is configured to perform matrix multiplication.

14. A device comprising:
a central processing unit configured to execute an application to issue a single transpose and load instruction specifying a plurality of blocks of data to be processed in a transposed form;
a processor array configured to process the transposed form of the data from at least one memory module circuit of the processor array; and
a control circuit configured to:
receive the single transpose and load instruction from the central processing unit; and
responsive to receiving the single transpose and load instruction, fetch the data by storing the transposed form of the data in the at least one memory module circuit without maintaining an intermediate representation of the transposed form of the data.

15. The device of claim 14 , wherein the plurality of blocks of data includes a first matrix that is column major and the transposed form of the data includes a second matrix that is row major, or the first matrix is row major and the second matrix is column major.

16. The device of claim 14 , wherein the control circuit includes fixed pattern remapping logic that transposes the data into the transposed form without maintaining the intermediate representation.

17. The device of claim 16 , wherein the fixed pattern remapping logic includes corner turn logic that transposes the data into the transposed form without maintaining the intermediate representation.

18. The device of claim 14 , wherein the control circuit transposes the data into the transposed form as part of the storing the transposed form of the data in the at least one memory module circuit without maintaining the intermediate representation.

19. The device of claim 14 , further comprising a data pool that maintains the plurality of blocks of the data, and the control circuit is configured to fetch the data from the data pool by storing the transposed form of the data in the at least one memory module circuit without maintaining an intermediate representation of the transposed form of the data.

20. The device of claim 19 , wherein the data pool is configured as external storage coupled to the processor array, and the at least one memory module circuit is configured as one or more registers of the processor array.

Assignees

• Advanced Micro Devices Inc

Inventors

• He Bin
• Mantor Michael John
• Emberling Brian
• Huang Liang
• Liu Chao

Classifications

• G06F15/8007

  single instruction multiple data [SIMD] multiprocessors · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F1/20

  Cooling means · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title