Method, apparatus, and system for calibrating a processor power level estimate

Patent metadata

Field	Value
Publication number	US-12228994-B2
Application number	US-202117472319-A
Country	US
Kind code	B2
Filing date	Sep 10, 2021
Priority date	Sep 10, 2021
Publication date	Feb 18, 2025
Grant date	Feb 18, 2025

Abstract

A system and method are described herein for estimating power usage of various components of a CPU and controlling voltage regulators based on the estimated power usage. The power estimates may be based on digital power meter readings at each component, on voltage information from a voltage regulator, and on other power information. This power information is transmitted over a mesh interconnect disposed throughout the CPU such that power estimation can be accurately calculated and used to control voltage regulators without being limited by external bus speeds. More of the power management processes and components may be disposed on the CPU and connected to the mesh interconnect. These power management processes include various calibrations, adjustments, and limits so as efficiently manage and use the more rapidly processed power estimations.

First claim

The invention claimed is:

1. A method for processor power management, comprising:
receiving first power information from a digital power meter (DPM) associated with a first component of a system-on-a-chip;
receiving second power information from a voltage regulator (VR) associated with the first component of the system-on-a-chip;
generating a power estimate value based on the first power information and the second power information; and
generating comparison information based on the first power information, the second power information, and a prior error representing a difference between a read power usage and an estimated power usage of the first component during a prior iteration of a calibration process, the first power information, the second power information, and the prior error all being direct inputs in generating the comparison information,
wherein a power to the first component or the system-on-a-chip is controlled based on the power estimate value and the comparison information.

2. The method of claim 1 , further comprising:
determining a correction value based on the comparison information;
generating a corrected first power information by applying the correction value to the first power information;
generating a corrected power estimate value based on the corrected first power information and the second power information; and
outputting the corrected power estimate value to a dynamic voltage and frequency scaling (DVFS) component to manage the power to the first component and/or a system power to the system-on-a-chip.

3. The method of claim 1 ,
wherein the DPM measures a first power usage of the first component, the first power information including the first power usage,
wherein the first component is a memory controller, a peripheral component interconnect express (PCIe) root complex, a processor core, a system management controller, or a common interface management controller.

4. The method of claim 1 , further comprising:
measuring, via the DPM, a first power usage from the first component, the first power information including the first power usage; and
scaling the first power usage based on at least one parameter of the component,
wherein the first component is a PCIe root complex and the at least one parameter is a PCIe vector, or
wherein the first component is a processor core and the at least one parameter is a voltage or a temperature of the processor core.

5. The method of claim 4 ,
wherein the first component is the PCIe root complex and the at least one parameter is the PCIe vector, and
wherein the PCIe vector includes a message signaled interrupt from a bus interface.

6. The method of claim 1 , further comprising:
estimating a power leakage of the first component;
scaling the power leakage based on a voltage or a temperature of the first component.

7. The method of claim 1 , further comprising:
measuring, via a DPM, a first power usage from the first component, the first power information including the first power usage; and
scaling the first power usage based on at least one parameter of the component,
wherein the first component is a PCIe root complex and the at least one parameter is a PCIe vector,
wherein the PCIe root complex is connected to the at least one processor core via a bus interface.

8. An apparatus comprising means for:
receiving first power information from a digital power meter (DPM) associated with a first component of a system-on-a-chip;
receiving second power information from a voltage regulator (VR) associated with the first component of the system-on-a-chip;
generating a power estimate value based on the first power information and the second power information; and
generating comparison information based on the first power information, the second power information, and a prior error representing a difference between a read power usage and an estimated power usage of the first component during a prior iteration of a calibration process, the first power information, the second power information, and the prior error all being direct inputs in generating the comparison information,
wherein a power to the first component or the system-on-a-chip is controlled based on the power estimate value and the comparison information.

9. The method of claim 2 , further comprising:
receiving at a proportional-integral-derivative (PID) controller the corrected power estimate; and
generating a control value at the PID controller;
calibrate a processor complex (PCP) power via the DVFS component based on the control value and/or the corrected power estimate.

10. The method of claim 1 , further comprising:
receiving third power information from another digital power meter (DPM) associated with a second component of the system-on-a-chip;
receiving fourth power information from another voltage regulator (VR) associated with the second component of the system-on-a-chip;
generating the power estimate value based on the first power information, the second power information, the third power information, and the fourth power information,
wherein at least one DPM is connected to each processor core of at least four processor cores of the system-on-a-chip.

11. A non-transitory computer readable medium storing one or more computer executable instructions that when executed on one or more processors causes the one or more processors to perform the method of:
receiving first power information from a digital power meter (DPM) associated with a first component of a system-on-a-chip;
receiving second power information from a voltage regulator (VR) associated with the first component of the system-on-a-chip;
generating a power estimate value based on the first power information and the second power information; and
generating comparison information based on the first power information, the second power information, and a prior error representing a difference between a read power usage and an estimated power usage of the first component during a prior iteration of a calibration process, the first power information, the second power information, and the prior error all being direct inputs in generating the comparison information,
wherein a power to the first component or the system-on-a-chip is controlled based on the power estimate value and the comparison information.

12. The method of claim 1 ,
wherein the system-on-a-chip further includes at least four processor cores and at least one memory controller,
wherein each processor core of the at least four processor cores and each of the at least one memory controller is connected to at least one corresponding, different DPM,
wherein separate power information from each corresponding, different DPM is combined together with the first power information and the second power information to calculate the power estimate value,
wherein a PCP power to at least one of the at least four processor cores or to the at least one memory controller is controlled by a dynamic voltage and frequency scaling (DVFS) component based on the power estimate value.

13. A power management circuit, comprising:
a first input receiving first power information from a digital power meter (DPM) connected to a first component of a system-on-a-chip;
a second input receiving second power information from a voltage regulator (VR) connected to the first component of the system-on-a-chip;
a power estimation component determining a power estimate value based on the first power information and the second power information and generating comparison information based on the first power information, the second power information, and a prior error representing a difference

Assignees

• Ampere Computing Llc

Inventors

• Raina Sarthak
• Patel Sanjay
• Tran Hoan
• Chatterjee Mitrajit
• Niraj Abhishek
• Raghunathan Anuradha

Classifications

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G01R21/133

  by using digital technique · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title