Load switch including back-to-back connected transistors

Patent metadata

Field	Value
Publication number	US-12224740-B2
Application number	US-202117404284-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	Nov 25, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

An apparatus includes a first drain/source region and a second drain/source region over a substrate, and a first gate adjacent to the first drain/source region, a second gate adjacent to the second drain/source region and a third gate between the first gate and the second gate, wherein the first drain/source region, the second drain/source region, the first gate, the second gate and the third gate form two back-to-back connected transistors.

First claim

What is claimed is:

1. A method comprising:
in an off-state of a load switch comprising two back-to-back connected transistors including a first gate, a second gate and a third gate formed over and in direct contact with a continuous dielectric layer, connecting the first gate and the second gate of the two back-to-back connected transistors to a first voltage potential lower than turn-on thresholds of the two back-to-back connected transistors, and connecting the third gate to a first source of the two back-to-back connected transistors; and
in an on-state of the load switch, connecting the first gate and the second gate of the two back-to-back connected transistors to a second voltage potential higher than the turn-on thresholds of the two back-to-back connected transistors, and connecting the third gate to a third voltage potential higher than the turn-on thresholds of the two back-to-back connected transistors.

2. The method of claim 1 , further comprising:
in the off-state of the load switch, connecting a fourth gate to a second source of the two back-to-back connected transistors; and
in the on-state of the load switch, connecting the fourth gate to the third voltage potential, wherein the two back-to-back connected transistors comprise:
the first source and the second source over a substrate;
the first gate adjacent to the first source;
the second gate adjacent to the second source;
a high voltage oxide region over the substrate;
a first gate dielectric layer formed between the high voltage oxide region and the first source; and
a second gate dielectric layer formed between the high voltage oxide region and the second source, and wherein:
the first gate is formed over the first gate dielectric layer and a first sidewall of the high voltage oxide region;
the second gate is formed over the second gate dielectric layer and a second sidewall of the high voltage oxide region; and
the third gate and the fourth gate are formed on top of the high voltage oxide region, and wherein the third gate and the fourth gate are separated from each other.

3. The method of claim 1 , further comprising:
in the off-state of the load switch, connecting a fourth gate to a second source of the two back-to-back connected transistors; and
in the on-state of the load switch, connecting the fourth gate to the third voltage potential, wherein the two back-to-back connected transistors comprise:
the first source and the second source over a substrate;
the first gate adjacent to the first source;
the second gate adjacent to the second source; and
an STI region over the substrate, and wherein:
the first gate extends from an edge of the first source and covers a first edge region of the STI region;
the second gate extends from an edge of the second source and covers a second edge region of the STI region; and
the third gate and the fourth gate are formed on top of the STI region, and wherein the third gate and the fourth gate are separated from each other.

4. The method of claim 1 , further comprising:
in the off-state of the load switch, connecting a fourth gate to a second source of the two back-to-back connected transistors; and
in the on-state of the load switch, connecting the fourth gate to the third voltage potential, wherein the two back-to-back connected transistors comprise:
the first source and the second source over a substrate;
the first gate adjacent to the first source;
the second gate adjacent to the second source;
a local oxidation of silicon (LOCOS) structure having a lower portion below a top surface of the first source and an upper portion over the top surface of the first source;
a first gate dielectric layer formed between the LOCOS structure and the first source; and
a second gate dielectric layer formed between the LOCOS structure and the second source, wherein:
the first gate is formed over the first gate dielectric layer and a first sidewall of the LOCOS structure;
the second gate is formed over the second gate dielectric layer and a second sidewall of the LOCOS structure; and
the third gate and the fourth gate are formed on top of the LOCOS structure, and wherein the third gate and the fourth gate are separated from each other.

5. The method of claim 1 , wherein:
a voltage coupled to the first source of the two back-to-back connected transistors is lower than a voltage coupled to a second source of the two back-to-back connected transistors.

6. The method of claim 1 , wherein:
the third gate is formed over a dielectric region between the first source and a second source of the two back-to-back connected transistors;
the first source and the second source are arranged in a symmetrical manner with respect to a center of the dielectric region; and
the third gate occupies a center of a top surface of the dielectric region.

7. The method of claim 1 , further comprising:
in the on-state of the load switch, connecting the first gate and the second gate of the two back-to-back connected transistors to the second voltage potential higher than the turn-on thresholds of the two back-to-back connected transistors prior to connecting the third gate to a third voltage potential higher than the turn-on thresholds of the two back-to-back connected transistors.

8. The method of claim 1 , further comprising:
in an off-state of the load switch comprising, connecting the third gate to the first source of the two back-to-back connected transistors prior to connecting the first gate and the second gate of the two back-to-back connected transistors to the first voltage potential lower than turn-on the thresholds of the two back-to-back connected transistors.

9. A controller comprising:
a first gate driver configured to apply a first voltage potential to a first gate of a load switch in an off-state of the load switch, and apply a second voltage potential to the first gate of the load switch in an on-state of the load switch, wherein the first voltage potential is lower than a turn-on threshold of a first switch of the load switch, and the second voltage potential is higher than the turn-on threshold of the first switch of the load switch;
a second gate driver configured to apply the first voltage potential to a second gate of the load switch in the off-state of the load switch, and apply the second voltage potential to the second gate of the load switch in the on-state of the load switch; and
a third gate driver configured to connect a third gate of the load switch to a first source of the load switch in the off-state of the load switch, and apply a third voltage potential to the third gate of the load switch in the on-state of the load switch, wherein the third voltage potential is higher than the turn-on threshold of the first switch of the load switch, wherein the first gate, the second gate and the third gate are formed over and in direct contact with a continuous dielectric layer.

10. The controller of claim 9 , further comprising:
a fourth gate driver configured to connect a fourth gate of the load switch to a second source of the load switch in the off-state of the load switch, and apply the third voltage potential to the fourth gate of the load switch in the on-state of the load switch.

11. The controller of claim 10 , wherein:
the load switch comprises two back-to-back connected transistors;
the first source and the second source are arranged in a symmetrical manner with respect to a dielectric region formed between the first source and the second source; and
the first gate and the second gate are arranged in a symmetrical manner with respect to the dielectric region.

12. The controller of claim 11 , wherein:
the f

Assignees

• Nuvolta Tech Hefei Co Ltd
• Nuvolta Technoloiges Heifei Co Ltd

Inventors

• Huang Jinbiao
• Lin John

Classifications

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D84/83125

  the IGFETs characterised by having shared source or drain regions · CPC title

• H10D84/835

  comprising LDMOS · CPC title

• H10D84/0128 Primary

  Manufacturing their channels · CPC title

• H10W10/0121

  in regions recessed from the surface, e.g. in trenches or grooves · CPC title