Array substrate including non-overlapping line segments and gate lines and manufacturing method therefor, and display device

Patent metadata

Field	Value
Publication number	US-12224289-B2
Application number	US-202017283425-A
Country	US
Kind code	B2
Filing date	Jun 19, 2020
Priority date	Jun 20, 2019
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

An array substrate includes gate lines, data lines and an insulating layer. The data lines all extend in a first direction, and the gate lines all extend in a second direction, the first direction intersecting the second direction. A data line includes first line segments and second line segments that all extend in the first direction and are arranged alternately. The second line segments are disposed at a side of the gate lines proximate to the base, and the first line segments are disposed at a side of the gate lines away from the base. There is no overlap among orthographic projections of the first line segments on the base and orthographic projections of the gate lines on the base. The insulating layer includes first vias. In the first direction, any two adjacent first line segments are electrically connected to a second fine segment through at least two first vias.

First claim

What is claimed is:

1. An array substrate, comprising:
a base, having a plurality of sub-pixel regions;
a plurality of gate lines and a plurality of data lines disposed on the base, wherein the plurality of data lines all extend in a first direction, and the plurality of gate lines all extend in a second direction, the first direction intersecting the second direction;
at least one of the plurality of data lines includes a plurality of first line segments and a plurality of second line segments that all extend in the first direction, the plurality of first lines segments and the plurality of second line segments being arranged alternately;
the plurality of second line segments are disposed at a side of the plurality of gate lines proximate to the base, and the plurality of first line segments are disposed at a side of the plurality of gate lines away from the base; and
orthographic projections of the plurality of first line segments on the base are non-overlapping with orthographic projections of the plurality of gate lines on the base;
an insulating layer disposed between the plurality of first line segments and the plurality of second line segments, the insulating layer including a plurality of first vias, wherein in the first direction, any two adjacent first line segments are electrically connected to a second line segment located between the two adjacent first line segments through at least two first vias; and
a plurality of pixel circuits disposed on the base, each pixel circuit being disposed in a sub-pixel region, and the pixel circuit being electrically connected to a gate line and a data line, wherein the pixel circuit includes a first switching transistor, a first gate of the first switching transistor and the gate line being disposed in a same layer and made of a same material, and a first source and a first drain of the first switching transistor and the plurality of first line segments being disposed in a same layer and made of a same material.

2. The array substrate according to claim 1 , wherein in the second direction, a width of a second line segment in the plurality of second line segments is greater than a width of a first line segment connected to the second line segment.

3. The array substrate according to claim 1 , wherein the first switching transistor is a top-gate thin film transistor; and the array substrate further comprises:
a plurality of first metal light-shielding patterns disposed on the base, wherein each first metal light-shielding pattern is disposed at a side, proximate to the base, of a first switching transistor in a corresponding pixel circuit, and an orthographic projection of a first active layer of the first switching transistor in the corresponding pixel circuit on the base is located within an orthographic projection of the first metal light-shielding pattern on the base; and
the plurality of second line segments and the plurality of first metal light-shielding patterns are disposed in a same layer and made of a same material, and the plurality of second line segments are insulated from the plurality of first metal light-shielding patterns.

4. The array substrate according to claim 3 , wherein the insulating layer further includes a plurality of second vias, and one of a first source and a first drain of the first switching transistor is electrically connected to the first metal light-shielding pattern through at least one second via.

5. The array substrate according to claim 3 , wherein in a thickness direction of the base, thicknesses of the plurality of second line segments are equal to thicknesses of the plurality of first metal light-shielding patterns.

6. The array substrate according to claim 1 , further comprising:
a plurality of pixel electrodes disposed on the base, each pixel electrode being disposed in a sub-pixel region, wherein the first source of the first switching transistor is electrically connected to the data line, the first drain of the first switching transistor is electrically connected to a pixel electrode, and the pixel electrode is disposed at a side of the first drain away from the base.

7. The array substrate according to claim 1 , further comprising:
a plurality of light-emitting devices disposed on the base, each light-emitting device being disposed in a sub-pixel region, and the light-emitting device being connected to a corresponding one of the plurality of pixel circuits.

8. The array substrate according to claim 7 , wherein the pixel circuit further includes a driving transistor, the driving transistor being a top-gate thin film transistor; and the array substrate further comprises:
a plurality of second metal light-shielding patterns disposed on the base, wherein each second metal light-shielding pattern is disposed at a side, proximate to the base, of a driving transistor in a corresponding pixel circuit, and an orthographic projection of a second active layer of the driving transistor on the base is located within an orthographic projection of the second metal light-shielding pattern on the base; and
the plurality of second line segments and the plurality of second metal light-shielding patterns are disposed in a same layer and made of a same material, and the plurality of second line segments are insulated from the plurality of second metal light-shielding patterns.

9. The array substrate according to claim 8 , further comprising:
a plurality of power lines, wherein the plurality of power lines all extend in the first direction, and the pixel circuit is electrically connected to a power line;
a power line of the plurality of power lines includes a plurality of third line segments and a plurality of fourth line segments that all extend in the first direction, the plurality of third line segments and the plurality of fourth line segments being arranged alternately;
orthographic projections of the plurality of third line segments on the base are non-overlapping with the orthographic projections of the plurality of gate lines on the base;
the plurality of third line segments and the plurality of first line segments are disposed in a same layer and made of a same material, and the plurality of fourth line segments and the plurality of second line segments are disposed in a same layer and made of a same material;
the insulating layer further includes a plurality of third vias; and in the first direction, any two adjacent third line segments are electrically connected to a fourth line segment located between the two adjacent third line segments through at least two third vias.

10. The array substrate according to claim 9 , wherein in the second direction, a width of a fourth line segment in the plurality of fourth line segments is greater than a width of a third line segment connected to the fourth line segment.

11. The array substrate according to claim 9 , wherein the power line is electrically connected to a second source of a driving transistor in a corresponding pixel circuit, and a second drain of the driving transistor is electrically connected to an anode of a corresponding light-emitting device.

12. The array substrate according to claim 1 , wherein the insulating layer includes a buffer layer and an interlayer dielectric layer that are stacked on the base.

13. A display device, comprising the array substrate according to claim 1 .

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Liu Ning
• Song Wei
• Hu Yingbin
• Wang Qinghe
• Zhang Feng
• Liu Chongchong
• Zhou Bin

Classifications

• H10D30/6746

  Amorphous silicon · CPC title

• H10D30/6745

  Polycrystalline or microcrystalline silicon · CPC title

• H10D30/6731

  Top-gate only TFTs · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title