Address signal transmission circuit, address signal transmission method and storage system

Patent metadata

Field	Value
Publication number	US-12224039-B2
Application number	US-202318163323-A
Country	US
Kind code	B2
Filing date	Feb 2, 2023
Priority date	Aug 5, 2022
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

An address signal transmission circuit includes a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, where the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal; and a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, where the selection circuit inverts the second address signal to obtain the address inverted signal.

First claim

What is claimed is:

1. An address signal transmission circuit, comprising:
a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, wherein the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal; and
a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, wherein the selection circuit inverts the second address signal to obtain the address inverted signal;
wherein the transmission control circuit is further configured to acquire a number of changed bits of address data in the first address signal and the second address signal and generate the inversion flag signal based on a relation between the number of changed bits and a predetermined value, wherein the number of changed bits of the address data is N, and the predetermined value satisfies M=N/2+1, M being the predetermined value and N being a positive integer; and
the selection circuit is further configured to, in a case where the number of changed bits is greater than or equal to the predetermined value, invert the second address signal to obtain the address inverted signal and output the address inverted signal, and in a case where the number of changed bits is smaller than the predetermined value, directly output the second address signal;
wherein the transmission control circuit comprises:
a latch sub-circuit, connected to the address bus, and configured to latch and output a received address signal; and
a comparison and determination sub-circuit, connected to the address bus and configured to acquire the second address signal, connected to the latch sub-circuit and configured to acquire the first address signal latched in the previous time, wherein the comparison and determination sub-circuit is configured to acquire the number of changed bits according to the first address signal and the second address signal, and compare the number of changed bits with the predetermined value to generate the inversion flag signal.

2. The address signal transmission circuit of claim 1 , wherein the latch sub-circuit comprises a latch, configured to latch and output the received address signal; and the transmission control circuit further comprises a delay sub-circuit, connected between the address bus and the latch, and configured to control a time when the address signal on the address bus is transmitted to the latch.

3. The address signal transmission circuit of claim 1 , wherein the latch sub-circuit comprises a register, a clock control end of the register being configured to receive a clock signal, and the register being connected to the address bus and configured to, in response to a trigger edge of the clock signal, latch and output the received address signal.

4. The address signal transmission circuit of claim 1 , wherein the comparison and determination sub-circuit comprises:
a first comparison sub-circuit, connected to the address bus and the latch sub-circuit, and configured to acquire the number of changed bits; and
a second comparison sub-circuit, connected to the first comparison sub-circuit, and configured to receive the number of changed bits, compare the number of changed bits with the predetermined value, and generate the inversion flag signal.

5. The address signal transmission circuit of claim 1 , wherein
in a case where the number of changed bits is greater than or equal to the predetermined value, the comparison and determination sub-circuit generates the inversion flag signal having a first level; and
in a case where the number of changed bits is smaller than the predetermined value, the comparison and determination sub-circuit generates an inversion flag signal having a second level, wherein the inversion flag signal having the first level is valid and the inversion flag signal having the second level is invalid.

6. The address signal transmission circuit of claim 5 , wherein
the selection circuit is configured to, in response to the inversion flag signal having the first level, invert the second address signal to obtain the address inverted signal, and output the address inverted signal; and
the selection circuit is configured to, in response to inversion flag signal having the second level, directly output the second address signal.

7. The address signal transmission circuit of claim 6 , wherein the selection circuit comprises N selection sub-circuits, each of the selection sub-circuits being configured to receive single-bit address data in the second address signal, each of the selection sub-circuits being connected to the transmission control circuit, and each of the selection sub-circuits being configured to, in response to the inversion flag signal, determine whether the corresponding single-bit address signal in the second address signal is to be inverted.

8. The address signal transmission circuit of claim 7 , wherein each of the selection sub-circuits comprises:
a first inversion sub-circuit, configured to receive the corresponding single-bit address data in the second address signal, and in response to the inversion flag signal having the first level, invert the single-bit address data to obtain single-bit address inverted data, and output the single-bit address inverted data; and
a first transmission sub-circuit, configured to receive the single-bit address data, and in response to the inversion flag signal having the second level, output the single-bit address data.

9. The address signal transmission circuit of claim 8 , wherein the first inversion sub-circuit comprises:
a first switch and a first inverter, the first switch being connected between the address bus and an input end of the first inverter, wherein the first switch is configured to be turned on in response to the inversion flag signal having the first level, and to be turned off in response to the inversion flag signal having the second level.

10. The address signal transmission circuit of claim 8 , wherein the first inversion sub-circuit comprises:
the first switch and the first inverter, the first switch being connected to an output end of the first inverter, the input end of the first inverter being connected to the address bus,
wherein the first switch is configured to be turned on in response to the inversion flag signal having the first level, and to be turned off in response to the inversion flag signal having the second level.

11. The address signal transmission circuit of claim 8 , wherein the first transmission sub-circuit comprises:
a first transmission gate, an input end of the first transmission gate receiving the single-bit address data, and a control end thereof receiving the inversion flag signal;
wherein the first transmission gate is configured to be turned off in response to the inversion flag signal having the first level, and to be turned on in responses to the inversion flag signal having the second level, so as to output the single-bit address data.

12. The address signal transmission circuit of claim 1 , further comprising:
a delay circuit, the delay circuit being connected between the selection circuit and the address bus, and configured to control the time when the second address signal is transmitted to the selection circu

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Kangling

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/10

  Decoders · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C11/408

  Address circuits · CPC title

• G11C11/4063

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing · CPC title