Memory system

Patent metadata

Field	Value
Publication number	US-12224030-B2
Application number	US-202217987435-A
Country	US
Kind code	B2
Filing date	Nov 15, 2022
Priority date	Dec 17, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

First claim

What is claimed is:

1. A memory system, comprising:
a memory controller; and
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device; and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;

wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address; and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;

wherein the memory controller or the semiconductor memory device is configured to:
send the data to be read or write and second check data for error detection of the data to the other of the memory controller or the semiconductor memory device; and
the other of the memory controller or the semiconductor memory device is configured to:
when receiving the data and the second check data, use the second check data to perform error detection of the data, and send third response information indicating that no error has been detected in the data to the memory controller and the semiconductor memory device.

2. The memory system as claimed in claim 1 , wherein the semiconductor memory device is configured to:
when an error is detected in the command or the address, send second response information indicating that an error has been detected in the command or the address to the memory controller;
wherein the memory controller is configured to:
when receiving the second response information from the semiconductor memory device, re-send the command and the address to the semiconductor memory device.

3. The memory system as claimed in claim 1 , wherein:
the other of the memory controller or the semiconductor memory device is configured to:
when an error is detected in the data, send fourth response information indicating that an error has occurred in the data to the memory controller or the semiconductor memory device; and
wait for a re-sending of the data from the memory controller or the semiconductor memory device until a specific time duration elapses.

4. The memory system as claimed in claim 3 , wherein:
the memory controller or the semiconductor memory device is configured to:
when receiving the fourth response information, re-send the data and the second check data corresponding to the data to the other of the memory controller or the semiconductor memory device.

5. The memory system as claimed in claim 3 , wherein:
the other of the memory controller or the semiconductor memory device is configured to:
terminate the waiting for the data to be re-sent when the data is not re-sent from the memory controller or the semiconductor memory device until the specific time duration has elapsed.

6. The memory system as claimed in claim 1 , wherein the semiconductor memory device further comprises a plurality of memory banks accessed in an interleaved manner.

7. The memory system as claimed in claim 1 , wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
stop the execution of the update by re-sending the command, the address, or the data from the memory controller until no error is detected.

8. The memory system as claimed in claim 1 , wherein when the semiconductor memory device is configured to generate an update request signal internally for executing an update, the semiconductor memory device is configured to:
in the duration between the generation of the update request signal and the execution of the update,
upon an error being detected in the command, the address, or the data received from the memory controller,
send fifth response information indicating that the update is executed to the memory controller, and
execute the update.

9. The memory system as claimed in claim 1 , wherein the semiconductor memory device is a pseudo-static random access memory.

10. A memory system, comprising:
a memory controller;
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device; and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;

wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address; and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;

a request control part, generating a transform signal upon receiving a request for writing to or reading from the semiconductor memory device from a host device, wherein the transform signal transforms a transmitting mode of an address data signal sending and receiving between the memory controller and the semiconductor memory device; and
a first serial control part, transforming the transmitting mode of the address data signal based on the transform signal.

11. The memory system as claimed in claim 10 , wherein the first serial control part comprises:
a first serializer/deserializer, serializing or deserializing the address data signal based on the transform signal; and
a first error control part, using the command and the address to generate the first check data.

12. The memory system as claimed in claim 11 , wherein the first serializer/deserializer is configured to:
when the request control part receives a write request, upon the transform signal being input from the request control part, generate a write command and the address, and send the write command and the address to the first error control part;
in response to the first check data of the generated write command and the address being input from the first error control part, send the generated write command, the address and the first check data to the semiconductor memory device as the address data signal; and
when receiving the first response information indicating that no error has been detected in the generated write command and the address from the semiconductor memory device as the address data signal, output data-to-be-written received from the host device to the first error control part.

13. The memory system as claimed in claim 10 , wherein the first error contro

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Sato Takahiko

Classifications

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1063

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title