Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays

Patent metadata

Field	Value
Publication number	US-12223994-B2
Application number	US-202418606333-A
Country	US
Kind code	B2
Filing date	Mar 15, 2024
Priority date	Apr 20, 2016
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

First claim

We claim:

1. A method of forming a ferroelectric transistor, comprising:
forming gate dielectric material configured as a first container, the first container having a first opening extending into the dielectric material and being defined by a first inner bottom surface and a first inner sidewall surface extending orthogonally relative to the first inner bottom surface;
forming a metal-containing material configured as a second container nested within said first opening, the second container having a second opening extending into the metal containing material and being defined by a second inner bottom surface with an area less than the first inner surface and having a second inner sidewall surface extending orthogonally relative to the second inner;
forming a ferroelectric material configured as a third container nested within the second opening, the third container having a third inner bottom surface with an area less than the second inner surface and having a third inner sidewall surface extending orthogonally relative to the third inner bottom surface;
forming a gate material within the third container, wherein a common sidewall surface extends orthogonally relative to the first, second and third inner bottom surfaces; and
forming an insulative sidewall spacer material along the common sidewall surface in direct physical contact with each of the metal-containing material, the gate dielectric material, the ferroelectric material and the gate material.

2. The method of claim 1 wherein the first, second and third containers are elbow-shaped.

3. The method of claim 1 wherein an edge of the second container is inset relative to an edge of the first container.

4. The method of claim 3 wherein an edge of the third container is inset relative to an edge of the first container by about a same amount as the edge of the second container is inset relative to the edge of the first container.

5. The method of claim 3 wherein an edge of the third container is inset relative to an edge of the first container by a greater amount than the edge of the second container is inset relative to the edge of the first container.

6. The method of claim 3 wherein an edge of the third container is inset relative to an edge of the first container by about a lesser amount than the edge of the second container is inset relative to the edge of the first container.

Assignees

• Micron Technology Inc

Inventors

• Ramaswamy Durai Vishak Nirmal
• Kinney Wayne

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• G11C11/2257

  Word-line or row circuits · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title

• H10B53/30

  characterised by the memory core region · CPC title