Display substrate, display panel and display device

Patent metadata

Field	Value
Publication number	US-12223908-B2
Application number	US-202218262598-A
Country	US
Kind code	B2
Filing date	Aug 24, 2022
Priority date	Sep 30, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A display substrate includes a pixel driving circuit, which includes a driving circuit, a storage circuit and a reset circuit. The reset circuit is electrically connected to a first terminal of the driving circuit. The driving circuit is used to conduct a path between the first terminal and a second terminal of the driving circuit under the control of a potential at its control terminal. The storage circuit is electrically connected to the control terminal of the driving circuit. The reset circuit includes a first capacitor. The storage circuit includes a second capacitor. An area of an overlap between orthographic projections of a first electrode plate and a second electrode plate of the first capacitor on the base substrate is smaller than that of the second capacitor on the base substrate.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate;
a first semiconductor layer disposed on the base substrate;
a first conductive layer disposed on a side of the first semiconductor layer away from the base substrate; and
a second conductive layer disposed on a side of the first conductive layer away from the base substrate,
wherein the display substrate further comprises a pixel driving circuit disposed on the base substrate, the pixel driving circuit comprises a driving circuit, a storage circuit and a reset circuit, wherein the reset circuit is electrically connected to a first terminal of the driving circuit or a second terminal of the driving circuit, and is configured to initialize a potential at the first terminal of the driving circuit or a potential at the second terminal of the driving circuit in an initialization stage; the driving circuit is configured to conduct a path between the first terminal of the driving circuit and the second terminal of the driving circuit under control of a potential at a control terminal of the driving circuit; and the storage circuit is electrically connected to the control terminal of the driving circuit and is configured to store electrical energy; and
wherein the reset circuit comprises a first capacitor, the storage circuit comprises a second capacitor, the first capacitor comprises a first electrode plate and a second electrode plate disposed opposite to the first electrode plate, the second capacitor comprises a first electrode plate and a second electrode plate disposed opposite to the first electrode plate, the first electrode plate of the first capacitor and the first electrode plate of the second capacitor are located in the first conductive layer, and the second electrode plate of the first capacitor and the second electrode plate of the second capacitor are located in the second conductive layer; an orthographic projection of the first electrode plate of the first capacitor on the base substrate and an orthographic projection of the first electrode plate of the second capacitor are spaced from each other on the base substrate, an orthographic projection of the second electrode plate of the first capacitor on the base substrate and an orthographic projection of the second electrode plate of the second capacitor are spaced from each other on the base substrate, the orthographic projection of the first electrode plate of the first capacitor on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the base substrate, and the orthographic projection of the first electrode plate of the second capacitor on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate of the second capacitor on the base substrate, wherein an area of the overlap between the orthographic projection of the first electrode plate of the first capacitor on the base substrate and the orthographic projection of the second electrode plate of the first capacitor on the base substrate is smaller than an area of the overlap between the orthographic projection of the first electrode plate of the second capacitor on the base substrate and the orthographic projection of the second electrode plate of the second capacitor on the base substrate, and a ratio of the area of the overlap between the orthographic projection of the first electrode plate of the second capacitor on the base substrate and the orthographic projection of the second electrode plate of the second capacitor on the base substrate to the area of the overlap between the orthographic projection of the first electrode plate of the first capacitor on the base substrate and the orthographic projection of the second electrode plate of the first capacitor on the base substrate is within a range of 5 to 20.

2. The display substrate of claim 1 , further comprising a first light-emitting control line, disposed on the base substrate and configured to supply a first light-emitting control signal to the pixel driving circuit,
wherein the first light-emitting control line is located in the first conductive layer, and a part of the first light-emitting control line overlapping with the second electrode plate of the first capacitor forms the first electrode plate of the first capacitor.

3. The display substrate of claim 2 , wherein the pixel driving circuit comprises a first light-emitting control circuit and a second light-emitting control circuit, the first light-emitting control circuit comprises a first transistor, the second light-emitting control circuit comprises a second transistor, the first transistor comprises a first gate, the second transistor comprises a second gate, and the first light-emitting control line applies the first light-emitting control signal to the first gate, the second gate, and the first electrode plate of the first capacitor.

4. The display substrate of claim 3 , wherein a part of the first light-emitting control line overlapping with the first semiconductor layer forms the first gate, and another part of the first light-emitting control line overlapping with the first semiconductor layer forms the second gate; and the first light-emitting control line further comprises a widened portion, the widened portion is located between the first gate and the second gate in a first direction, and a size of the widened portion in a second direction is greater than a size of each of the first gate and the second gate in the second direction, wherein the first light-emitting control line extends in the first direction, and the second direction intersects with the first direction; and
at least a part of the widened portion forms the first electrode plate of the first capacitor.

5. The display substrate of claim 4 , wherein the orthographic projection of the second electrode plate of the first capacitor on the base substrate covers an orthographic projection of the widened portion on the base substrate; and/or
an area of the orthographic projection of the first electrode plate of the second capacitor on the base substrate is greater than an area of the orthographic projection of the widened portion on the base substrate; and/or,
an area of the orthographic projection of the second electrode plate of the second capacitor on the base substrate is greater than an area of the orthographic projection of the second electrode plate of the first capacitor on the base substrate.

6. The display substrate of claim 1 , wherein the ratio of the area of the overlap between the orthographic projection of the first electrode plate of the second capacitor on the base substrate and the orthographic projection of the second electrode plate of the second capacitor on the base substrate to the area of the overlap between the orthographic projection of the first electrode plate of the first capacitor on the base substrate and the orthographic projection of the second electrode plate of the first capacitor on the base substrate is within a range of 8 to 10.

7. The display substrate of claim 6 , wherein the second electrode plate of the second capacitor comprises a through hole exposing at least a part of the first electrode plate of the second capacitor, and a ratio of an area of the orthographic projection of the second electrode plate of the first capacitor on the base substrate to an area of an orthographic projection of the through hole on the base substrate is within a range of 1.1 to 5.

8. The display substrate of claim 1 , further comprising a light-emitting element reset line located in the first conductive layer and a light-emitting element disposed on the base substrate, wherein the pixel driving circuit comprises a first initialization circuit config

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shan Zhenzhen
• Liu Libin
• Lu Jiangnan
• Shi Shiming

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title