Pixel circuit and driving method thereof, display panel and display apparatus

US12223903B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12223903-B2
Application numberUS-202318534793-A
CountryUS
Kind codeB2
Filing dateDec 11, 2023
Priority dateJun 13, 2018
Publication dateFeb 11, 2025
Grant dateFeb 11, 2025

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A pixel circuit, a display panel, a display apparatus and a driving method. The pixel circuit includes a data signal writing module, a driving module, a threshold compensation transistor, a first power voltage writing module and a light-emitting module, wherein the driving module includes a driving transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising: a data signal writing module; a driving module; a threshold compensation transistor; a first power voltage writing module; and a light-emitting module, wherein the driving module comprises a driving transistor, wherein: the first power voltage writing module is connected to a first light-emitting control signal terminal, a first power voltage terminal, a source of the driving transistor and a gate of the driving transistor, and the first power voltage writing module is configured to write a first power voltage signal of the first power voltage terminal to the source of the driving transistor under control of a first light-emitting control signal of the first light-emitting control signal terminal; the data signal writing module is connected to a writing control terminal, a data signal terminal and the source of the driving transistor, and the data signal writing module is configured to transmit a data signal of the data signal terminal to the source of the driving transistor under control of a writing control signal of the writing control terminal; the threshold compensation transistor has a gate connected to a first node, a source connected to the gate of the driving transistor and a drain connected to a drain of the driving transistor, and the threshold compensation transistor is configured to perform voltage compensation to the gate of the driving transistor in case that the first node is at a valid level; and the light-emitting module has a first terminal connected to the drain of the driving transistor and a second terminal connected to a second power voltage terminal, and wherein: a driving stage of the pixel circuit comprises a first initialization phase and a second initialization phase; and in the second initialization phase, the first light-emitting control signal is at a second level, and a second light-emitting control signal is at a first level. 2. The pixel circuit of claim 1 , wherein the threshold compensation transistor is an oxide transistor. 3. The pixel circuit of claim 1 , wherein the pixel circuit further comprises: a reference signal writing module connected to a reference control terminal, a reference signal terminal, the first light-emitting control signal terminal and the first node, and the reference signal writing module is configured to control potential of the first node according to a reference control signal of the reference control terminal and the first light-emitting control signal of the first light-emitting control signal terminal. 4. The pixel circuit of claim 3 , wherein the reference signal writing module comprises: a reference signal writing transistor having a gate connected to the reference control terminal, a source connected to the first node, and a drain connected to the reference signal terminal; and a first capacitor connected between the first light-emitting control signal terminal and the first node. 5. The pixel circuit of claim 1 , wherein the pixel circuit further comprises: a reset module connected to a reset control terminal, a reset potential terminal and the first terminal of the light-emitting module, and configured to reset the first terminal of the light-emitting module and the gate of the driving transistor under control of a reset control signal of the reset control terminal. 6. The pixel circuit of claim 5 , wherein the reset module comprises: a reset transistor having a gate connected to the reset control terminal, a source connected to the first terminal of the light-emitting module, and a drain connected to the reset potential terminal. 7. The pixel circuit according to claim 6 , wherein a second power voltage of the second power voltage terminal is lower than a reset potential of the reset potential terminal. 8. The pixel circuit of claim 1 , wherein the pixel circuit further comprises: a light-emitting control module connected to a second light-emitting control signal terminal, the drain of the drive transistor and the first terminal of the light-emitting module, and configured to drive the light-emitting module to emit light under control of the second light-emitting control signal of the second light-emitting control signal terminal. 9. The pixel circuit of claim 8 , wherein the light-emitting control module comprises: a light-emitting control transistor having a gate connected to the second light-emitting control signal terminal, a source connected to the drain of the driving transistor, and a drain connected to the first terminal of the light-emitting module. 10. The pixel circuit of claim 1 , wherein the data signal writing module comprises: a data writing transistor having a gate connected to a data writing control terminal, a source connected to the data signal terminal, and a drain connected to the source of the drive transistor. 11. The pixel circuit of claim 1 , wherein the first power voltage writing module comprises: a first power voltage writing transistor having a gate connected to the first light-emitting control signal terminal, a source connected to the first power voltage terminal, and a drain connected to the source of the driving transistor. 12. The pixel circuit of claim 1 , wherein the driving module further comprises: a second capacitor connected between the first power voltage terminal and the gate of the driving transistor. 13. The pixel circuit of claim 1 , wherein the light-emitting module comprises: an organic light-emitting diode (OLED), an anode of the OLED serving as the first terminal of the light-emitting module, and a cathode of the OLED serving as the second terminal of the light-emitting module. 14. A display panel comprising the pixel circuit of claim 1 . 15. A method for driving the pixel circuit of claim 1 , comprising: in a data writing and threshold compensation phase, writing the data signal of the data signal terminal to the source of the driving transistor, the writing control signal of the writing control terminal being at the first level, and the reference control signal of the reference control terminal being hopped from the first level to the second level, level of the first light-emitting control signal being hopped from the first level to the second level, level of the first node being raised, and potential of the gate of the driving transistor being compensated under control of the first node; and in a light-emitting phase, directing a driving current of the driving transistor to the light-emitting module to drive the light-emitting module to emit light, wherein the second light-emitting control signal of the second light-emitting control signal terminal is at the first level. 16. The method of claim 15 , wherein: the pixel circuit further comprises: a reference signal writing module connected to the reference control terminal, the reference signal terminal, the first light-emitting control signal terminal, and the first node; and the method further comprises the first initialization phase and the second initialization phase: in the first initialization phase, in which the reference control signal of the reference control terminal is at the first level, transmitting the reference signal of the reference signal terminal to the first node; and in the second initialization phase, transitioning the reference control signal of the reference control terminal from the first level to the second level, transitioning the level of the first light-emitting control signal from the first level to the second level, and raising the level of the first node. 17. The method of claim 16 , wherein th

Assignees

Inventors

Classifications

  • Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

  • Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

  • Temperature compensation · CPC title

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12223903B2 cover?
A pixel circuit, a display panel, a display apparatus and a driving method. The pixel circuit includes a data signal writing module, a driving module, a threshold compensation transistor, a first power voltage writing module and a light-emitting module, wherein the driving module includes a driving transistor.
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Feb 11 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).