Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12223900-B2
Application number	US-202218272811-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Jul 29, 2022
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.

First claim

The invention claimed is:

1. A display substrate, comprising: a display area and a non-display area, wherein the display area is provided with pixel circuits arranged in an array, and the display area is divided into M partitions along a first direction; a pixel circuit comprises a writing transistor, an anode reset transistor, a gate control transistor, a light emitting transistor, and a first scan signal line, a second scan signal line, a third scan signal line and a light emitting signal line that extend along a second direction, wherein the first scan signal line is electrically connected with the writing transistor, the second scan signal line is electrically connected with the gate control transistor, the third scan signal line is electrically connected with the anode reset transistor, the light emitting signal line is connected with the light emitting transistor, and M is a positive integer greater than or equal to 2;
the non-display area is provided with a light emitting driving circuit group, a control driving circuit group, a reset driving circuit group, a first light emitting clock signal line to a fourth light emitting clock signal line, a first control clock signal line to a fourth control clock signal line, and a first reset clock signal line to a fourth reset clock signal line;
the light emitting driving circuit group comprises M light emitting driving circuits, an i-th light emitting driving circuit is connected with a light emitting signal line in a pixel circuit in an i-th partition, an odd-numbered light emitting driving circuit is electrically connected with the first light emitting clock signal line and the second light emitting clock signal line, and an even-numbered light emitting driving circuit is connected with the third light emitting clock signal line and the fourth light emitting clock signal line, where i=1, 2, . . . , M;
and/or, the control driving circuit group comprises M control driving circuits, an i-th control driving circuit is connected with a second scan signal line in the pixel circuit in the i-th partition, an odd-numbered control driving circuit is electrically connected with the first control clock signal line and the second control clock signal line, and an even-numbered control driving circuit is connected with the third control clock signal line and the fourth control clock signal line;
and/or, the reset driving circuit group comprises M reset driving circuits, an i-th reset driving circuit is connected with a third scan signal line in the pixel circuit in the i-th partition, an odd-numbered reset driving circuit is electrically connected with the first reset clock signal line and the second reset clock signal line, and an even-numbered reset driving circuit is connected with the third reset clock signal line and the fourth reset clock signal line.

2. The display substrate according to claim 1 , wherein a first partition comprises pixel circuits of a first row to pixel circuits of an N 1 -th row, a j-th partition comprises pixel circuits of an (N j−1 +1)-th row to pixel circuits of an N j -th row, j=2, . . . , M;
a light emitting driving circuit comprises light emitting shift registers, wherein a light emitting shift register comprises a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal and a fourth signal output terminal;
a first light emitting driving circuit comprises: N 1 /4 cascaded light emitting shift registers, a cascaded signal output terminal of a light emitting shift register of an x-th stage is connected with a signal input terminal of a light emitting shift register of an (x+1)-th stage in the first light emitting driving circuit; a first signal output terminal, a second signal output terminal, a third signal output terminal and a fourth signal output terminal of the light emitting shift register of the x-th stage in the first light emitting driving circuit are respectively connected with light emitting signal lines of pixel circuits in a (4x−3)-th row, pixel circuits in a (4x−2)-th row, pixel circuits in a (4x−1)-th row and pixel circuits in a 4x-th row, where x=1, 2, . . . , N 1 /4;
a j-th light emitting driving circuit comprises (N j −N j−1 )/4 cascaded light emitting shift registers, a cascaded signal output terminal of a light emitting shift register of a y-th stage is connected with a signal input terminal of a light emitting shift register of a (y+1)-th stage in the j-th light emitting driving circuit; a first signal output terminal, a second signal output terminal, a third signal output terminal and a fourth signal output terminal of the light emitting shift register of the y-th stage in the j-th light emitting driving circuit are respectively connected with light emitting signal lines of pixel circuits in an (N j−1 +4y−3)-th row, pixel circuits in an (N j−1 +4y−2)-th row, pixel circuits in an (N j−1 +4y−1)-th row, pixel circuits in an (N j−1 +4y)-th row, where y=1, 2, . . . , (N j −N j−1 )/4.

3. The display substrate according to claim 2 , wherein the light emitting shift register further comprises: a first clock signal terminal and a second clock signal terminal;
a first clock signal terminal in a light emitting shift register in an odd-numbered light emitting driving circuit is connected with one of the first light emitting clock signal line and the second light emitting clock signal line, a second clock signal terminal in the light emitting shift register in the odd-numbered light emitting driving circuit is connected with the other of the first light emitting clock signal line and the second light emitting clock signal line, and first clock signal terminals in adjacent light emitting shift registers are connected with different light emitting clock signal lines;
a first clock signal terminal in a light emitting shift register in an even-numbered light emitting driving circuit is connected with one of the third light emitting clock signal line and the fourth light emitting clock signal line, a second clock signal terminal in the light emitting shift register in the even-numbered light emitting driving circuit is connected with the other of the third light emitting clock signal line and the fourth light emitting clock signal line, and first clock signal terminals in adjacent light emitting shift registers are connected with different light emitting clock signal lines.

4. The display substrate according to claim 2 , wherein a control driving circuit comprises: control shift registers, a control shift register comprises: a cascaded signal output terminal, a signal input terminal, a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal;
a first control driving circuit comprises N 1 /4 cascaded control shift registers, a cascaded signal output terminal of a control shift register of an x-th stage is connected with a signal input terminal of a control shift register of an (x+1)-th stage in the first control driving circuit; a first signal output terminal, a second signal output terminal, a third signal output terminal and a fourth signal output terminal of the control shift register of the x-th stage in the first control driving circuit are respectively connected with second scan signal lines of pixel circuits in a (4x−3)-th row, pixel circuits in a (4x−2)-th row, pixel circuits in a (4x−1)-th row and pixel circuits in a 4x-th row, where x=1, 2, . . . , N 1 /4;
a j-th control driving circuit comprises (N j −N j−1 )/4 cascaded control shift registers, a cascaded signal output terminal of a control shift register of a y-th stage is connected with a signal input terminal of a control shift register of a (y+1)-th stage in the j-th control driving circuit; a first signal output terminal, a second signal output te

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yuan Zhidong
• Li Yongqian
• Yuan Can
• Wu Liu
• Liu Xiuting
• Ding Luke
• Xu Cheng
• Liu Miao
• Yao Xing

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title