Micro display controlling system

Patent metadata

Field	Value
Publication number	US-12223879-B2
Application number	US-202418605873-A
Country	US
Kind code	B2
Filing date	Mar 15, 2024
Priority date	Sep 18, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A micro display controlling system includes a data interface, a data decoder, a memory-write controller, a frame-memory controller including at least two frame memories, at least one color-display panel, a data processor including at least two data formatting processors, and a data output interface including at least two sub-output interfaces.

First claim

What is claimed is:

1. A micro display controlling system, comprising:
a data interface configured to provide image data;
a data decoder, coupled to the data interface, to receive and decode the image data as single-color data frame;
a memory-write controller configured to receive and restore the frame data from the data decoder;
a frame-memory controller, comprising:
at least two frame memories, each configured to receive a different one of the single-color data frames from the memory-write controller, wherein a first frame memory configured to receive and store, from the memory-write controller, a first single-color data frame corresponding to a first color, and a second frame memory configured to received and store, from the memory-write controller, a second single-color data frame corresponding to a second color;

at least one color-display panel;
a data processor, comprising:
at least two data formatting processors, each data formatting processor is further configured to process the single-color data frame and provides a panel controlling signal and processed frame data, wherein each panel controlling signal is configured to control the color-display panel; and

a data output interface, comprising at least two sub-output interfaces, each coupled to one of the data formatting processors, wherein each of the data formatting processors provides the panel controlling signal and the processed frame data to the output interface, the output interface further providing the panel controlling signal and the processed frame data to the color display panel.

2. The micro display controlling system according to claim 1 , further comprising a register controller, coupled to the memory-write controller and the data interface and decoder, the register controller configured to receive clock signal data from the processed frame data.

3. The micro display controlling system according to claim 2 , further comprising a panel timing and synchronization controller, coupled to receive the clock signal data from the first register controller, the panel timing and synchronization controller being configured to sort the processed frame data according to the clock signal data.

4. The micro display controlling system according to claim 3 , wherein the panel timing and synchronization controller is coupled to the data processer and further configured to provide the processed frame data to the data processor in an order corresponding to the clock signal data.

5. The micro display controlling system according to claim 4 , wherein the panel timing and synchronization controller is coupled to the at least one color-display panel and further configured to control data transmit timing of the at least one color-display panel.

6. The micro display controlling system according to claim 1 , wherein the number of the data formatting processors is the same as the number of the frame-memories.

7. The micro display controlling system according to claim 1 , the at least one color-display panel further comprising at least two display modules, the at least two display modules respectively coupled to the at least two sub-output interfaces, wherein, each of the display modules is further configured to receive the panel controlling signal and the processed frame data from the sub-output interface.

8. The micro display controlling system according to claim 7 , the display module further comprising,
a display control, coupled to the sub-output interface, configured to receive the panel controlling signal and the processed frame data from the sub-output interface;
a pixel driver array, coupled to the display control, configured to receive the processed frame data corresponding to the panel controlling signal; and
at least one micro light-emitting diode (LED) light,
wherein the pixel driver array is configured to control the at least one micro LED light in the display panel, corresponding to the processed frame data and the panel controlling signal, to turn the at least one micro LED light on or off.

9. The micro display controlling system according to claim 8 , wherein the display control comprising,
a data receiver, coupled to the data output interface, to receive processed frame data from the data output interface;
a scan controlling signal processor, coupled to the data receiver, to receive and convert the processed frame data into a column controlling signal and a row controlling signal;
a shift register coupled to the data receiver to receive processed frame data from the data receiver, the shift register configured to provide the processed frame data to the column driver and the row driver;
a second register controller coupled to the data receiver to receive the processed frame data and the data from the data receiver, the second register controller configured to verify a sort of the processed frame data according to the time series data;
a row driver, coupled to both the scan controlling signal processer and the shift register, configured to receive the row controlling signal and provide a corresponding row pixel signal to the pixel driver array; and
a column driver coupled to both the scan controlling signal processer and the shift register, configured to receive the column controlling signal and provide a correspond column pixel signal to the pixel driver array.

10. The micro display controlling system according to claim 1 , wherein, the decoded single-color data frame comprises a single color in red, green, or blue.

Assignees

• Jade Bird Display Shanghai Ltd

Inventors

• Li Qiming
• Ju Jing
• Liu Hongyun
• Li Chunming

Classifications

• G09G2370/00

  Aspects of data communication · CPC title

• G09G2360/12

  Frame memory handling · CPC title

• G09G2360/02

  Graphics controller able to handle multiple formats, e.g. input or output formats · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2320/02

  Improving the quality of display appearance · CPC title