Variable width interleaved coding for graphics processing

Patent metadata

Field	Value
Publication number	US-12223682-B2
Application number	US-202117357038-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Mar 19, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

Variable width interleaved coding for graphics processing is described. An example of an apparatus includes one or more processors including a graphic processor; and memory for storage of data including data for graphics processing, wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to receive a plurality of bitstreams from workgroups; perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups; perform variable interleaving of the bitstreams for each workgroup based at least in part on data requirements for decoding received from the decoder pipeline; and compact outputs for each of the workgroups into a contiguous stream of interleaved data.

First claim

What is claimed is:

1. An apparatus comprising:
one or more processors including a graphic processor; and
memory for storage of data including data for graphics processing;
wherein the graphics processor includes an encoder pipeline to provide variable width interleaved coding and a decoder pipeline to decode the variable width interleaved coding, and wherein the encoder pipeline is to:
receive a plurality of bitstreams from a plurality of workgroups;
perform parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups;
perform variable interleaving of the bitstreams for each workgroup of the plurality of workgroups, wherein a number of data elements that are interleaved for each workgroup in each of a plurality of iterations is based at least in part on current data requirements for decoding for each workgroup received from the decoder pipeline; and
compact interleaved bitstream outputs for each of the plurality of workgroups into a contiguous stream of interleaved data.

2. The apparatus of claim 1 , wherein the entropy encoding comprises Huffman coding.

3. The apparatus of claim 1 , wherein the received plurality of bitstreams include Single Instruction Multiple Data (SIMD) bitstreams.

4. The apparatus of claim 1 , wherein:
the encoder pipeline includes a plurality of parallel entropy encoders for each of the plurality of workgroups; and
the decoder pipeline includes a plurality of parallel entropy decoders for each of the plurality of workgroups.

5. The apparatus of claim 4 , wherein bitstream write patterns produced by the parallel entropy encoders for the plurality of workgroups are to be synchronized with bitstream read patterns of the parallel entropy decoders for the plurality of workgroups.

6. The apparatus of claim 1 , wherein the encoded bitstreams may be of variable lengths.

7. The apparatus of claim 6 , wherein a number of encoded bitstreams that are interleaved in the variable interleaving may vary with each iteration of the encoder pipeline.

8. The apparatus of claim 1 , wherein the decoder pipeline is to:
receive the contiguous data stream;
provide the current data requirements for decoding for each workgroup to the encoder pipeline;
separate the contiguous data stream into a plurality of sets of data based at least in part on the data requirements for decoding for each workgroup provided to the encoder pipeline; and
perform parallel entropy decoding of the plurality of sets of data for each workgroup to generate a plurality of bitstreams.

9. The apparatus of claim 8 , wherein the performance of parallel entropy decoding includes use of an entropy code lookup table.

10. The apparatus of claim 1 , wherein the encoder pipeline and the decoder pipeline utilize a kernel workgroup size that is equal to a target SIMD width.

11. One or more non-transitory computer-readable storage mediums having stored thereon executable computer program instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:
receiving a plurality of bitstreams from a plurality of workgroups at an encoder pipeline;
performing parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups;
performing variable interleaving of the bitstreams for each workgroup of the plurality of workgroups, wherein a number of data elements that are interleaved for each workgroup in each of a plurality of iterations is based at least in part on current data requirements for decoding received from a decoder pipeline; and
compacting interleaved bitstream outputs for each of the plurality of workgroups into a contiguous stream of interleaved data.

12. The one or more storage mediums of claim 11 , wherein:
the encoder pipeline includes a plurality of parallel entropy encoders for each of the plurality of workgroups; and
the decoder pipeline includes a plurality of parallel entropy decoders for each of the plurality of workgroups.

13. The one or more storage mediums of claim 11 , wherein the encoded bitstreams may be of variable lengths, and wherein a number of encoded bitstreams that are interleaved in the variable interleaving may vary with each iteration of the encoder pipeline.

14. The one or more storage mediums of claim 11 , wherein the instructions further include instructions for:
receiving the contiguous data stream at the decoder pipeline;
providing the current data requirements for decoding for each workgroup to the encoding pipeline;
separating the contiguous data stream into a plurality of sets of data based at least in part on the data requirements for decoding for each workgroup provided to the encoding pipeline; and
performing parallel entropy decoding of the plurality of sets of data for each workgroup to generate a plurality of bitstreams.

15. The one or more storage mediums of claim 14 , wherein performing parallel entropy decoding includes use of an entropy code lookup table.

16. A method comprising:
receiving a plurality of bitstreams from a plurality of workgroups at an encoder pipeline;
performing parallel entropy encoding on the bitstreams to generate a plurality of encoded bitstreams for each of the workgroups;
performing variable interleaving of the bitstreams for each workgroup of the plurality of workgroups, wherein a number of data elements that are interleaved for each workgroup in each of a plurality of iterations is based at least in part on current data requirements for decoding received from a decoder pipeline; and
compacting interleaved bitstream outputs for each of the workgroups into a contiguous stream of interleaved data.

17. The method of claim 16 , wherein:
the encoder pipeline includes a plurality of parallel entropy encoders for each of the plurality of workgroups; and
the decoder pipeline includes a plurality of parallel entropy decoders for each of the plurality of workgroups.

18. The method of claim 16 , wherein the encoded bitstreams may be of variable lengths, and wherein a number of encoded bitstreams that are interleaved in the variable interleaving may vary with each iteration of the encoder pipeline.

19. The method of claim 16 , further comprising:
receiving the contiguous data stream at the decoder pipeline;
providing the current data requirements for decoding for each workgroup to the encoding pipeline;
separating the contiguous data stream into a plurality of sets of data based at least in part on the data requirements for decoding for each workgroup provided to the encoding pipeline; and
performing parallel entropy decoding of the plurality of sets of data for each workgroup to generate a plurality of bitstreams.

20. The method of claim 19 , wherein performing parallel entropy decoding includes use of an entropy code lookup table.

Assignees

• Intel Corp

Inventors

• Junkins Stephen
• Kothandaraman Sreenivas
• Surti Prasoonkumar
• Pratapa Srihari
• Hux William
• Feit John

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title

• G06T9/005 Primary

  Statistical coding, e.g. Huffman, run length coding · CPC title

• G06T15/06

  Ray-tracing · CPC title

• G06T7/41

  based on statistical description of texture · CPC title