Memory interface for initalizing memory and method thereof

Patent metadata

Field	Value
Publication number	US-12223188-B2
Application number	US-202217748564-A
Country	US
Kind code	B2
Filing date	May 19, 2022
Priority date	Jan 6, 2022
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.

First claim

What is claimed is:

1. A memory interface for interfacing with a memory device, the memory interface comprising:
a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred,
wherein the pre-defined data is run-time data from an application running on a computer system including the memory device,
wherein the pre-defined data is stored in one or more registers associated with the computer system.

2. The memory interface of claim 1 , further comprising a cache connected to the control circuit, and the control circuit performs the initialize without using the cache.

3. The memory interface of claim 2 , further comprising a translation lookaside buffer (TLB) connected to the cache, and the control circuit performs the initialize without using the TLB.

4. The memory interface of claim 2 , further comprising a central processing unit (CPU) connected to the cache via a data bus and connected to the control circuit via a signal line separate from the data bus, and the control circuit determines the trigger event has occurred in response to receiving a trigger signal from the CPU through the signal line.

5. The memory interface of claim 4 , the control circuit performs the initialize without using the data bus.

6. The memory interface of claim 1 , wherein the memory is a dynamic random-access memory (DRAM).

7. The memory interface of claim 1 , wherein the control circuit is located within a scrub engine that is configured detect whether an error has occurred in original data in a given one of the memory locations, correct the original data into corrected data upon detecting the error, and write the corrected data to volatile memory.

8. The memory interface of claim 7 , wherein the scrub engine detects whether the error has occurred upon detection of an idle time or a powering on a computer system including the volatile memory.

9. The memory interface of claim 1 , wherein the trigger event indicates one of i) powering on of a computer system including a volatile memory and ii) identification of a request for initializing the one or more memory locations received from an application in the computer system.

10. The memory interface of claim 1 , wherein the control circuit is configured to initialise the one or more memory locations based on a status associated with each of the one or more memory locations, wherein the status indicates whether the initialization of a corresponding memory location among the one or more memory locations has already been performed.

11. The memory interface of claim 1 , wherein the control circuit is further configured to write first data associated with a first location in the memory device to a second location in the memory device, upon receiving a request for transferring the first data from the first location to the second location from an application in a computer system including the memory device.

12. A method for interfacing with a memory device, the method comprising:
determining, by a control circuit of a memory interface, whether a trigger event has occurred for initializing one or more memory locations in the memory device; and
initializing, by the control circuit, the one or more memory locations in the memory device with pre-defined data related upon determining the trigger event has occurred,
wherein the pre-defined data is run-time data from an application running on a computer system including the memory device,
wherein the pre-defined data is stored in one or more registers associated with the computer system.

13. The method of claim 12 , wherein the initializing is performed without using a cache connected to the control circuit.

14. The method of claim 13 , wherein the initializing is performed without using a translation lookaside buffer (TLB) connected to the cache.

15. The method of claim 13 , wherein the determining comprises the control circuit determining the trigger event has occurred in response to receiving a trigger signal through a signal line from a central processing unit (CPU) connected to the cache that is separate from a data bus connecting the CPU to the cache.

16. The method of claim 15 , wherein the initializing is performed without using the data bus.

17. The method of claim 12 , wherein the trigger event indicates identification of a request for initializing the one or more memory locations received from an application in the computer system.

18. A memory interface for interfacing with a memory device, the memory interface comprising:
a memory controller connected to the memory device;
a cache connected to the memory controller; and
a central processing unit (CPU) connected to the cache via a data bus and connected to the memory controller via signal line separate from the data bus,
wherein the memory controller initializes one or more memory locations of the memory device in response to receiving a trigger signal from the CPU via the signal line.

19. The memory interface of claim 18 , wherein the memory controller comprises a scrub engine to perform a scrub operation on the memory device, and the scrub engine performs the initializing of the one more memory locations.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Talanki Raghu Vamsi Krishna
• Khare Archita
• Ravikumar Rahul Tarikere
• So Jinin
• Lee Jonggeon

Classifications

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F11/106

  Correcting systematically all correctable errors, i.e. scrubbing · CPC title