Fault isolation and recovery of CPU cores for failed secondary asymmetric multiprocessing instance

Patent metadata

Field	Value
Publication number	US-12222830-B2
Application number	US-202318539996-A
Country	US
Kind code	B2
Filing date	Dec 14, 2023
Priority date	Dec 10, 2019
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

According to certain embodiments, a system includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components to perform operations including executing a software process of a secondary instance, the secondary instance running in parallel with a primary instance and associated with a plurality of cores including a bootstrap core, registering a non-maskable interrupt for the bootstrap core in the secondary instance, determining whether the secondary instance is in a fault state, wherein, if the secondary instance is in the fault state, halting the plurality of cores associated with the secondary instance, without impact to the primary instance, and recovering the bootstrap core by switching a context of the bootstrap core from the secondary instance to the primary instance via the non-maskable interrupt.

First claim

What is claimed is:

1. A system, comprising:
one or more processors; and
one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components of the system to perform operations comprising:
issuing, by a primary instance, a central processing unit (CPU) hotplug from a user space;
delivering, by the CPU hotplug, a non-maskable interrupt (NMI) to a bootstrap core;
initiating, by the NMI, a recovery sequence to switch a context of the bootstrap core from a secondary instance to the primary instance;
executing the bootstrap core into an online state in the primary instance; and
recovering, by the primary instance, a plurality of CPU cores from the secondary instance.

2. The system of claim 1 , wherein initiating, by the NMI, a recovery sequence to switch a context of the bootstrap core from a secondary instance to the primary instance comprises:
writing a trampoline page directory table address to a control register of the secondary instance; and
branching execution of the bootstrap core to a real mode machine start address of the primary instance.

3. The system of claim 2 , wherein branching the execution of the bootstrap core to the real mode machine start address of the primary instance is performed by leveraging an advanced power management (APM) restart hook.

4. The system of claim 1 , the operations further comprising issuing, by the primary instance, the CPU hotplug from the user space in response to detecting, by the primary instance, that the secondary instance is in a fault or panic state.

5. The system of claim 4 , the operations further comprising presuming that the plurality of CPU cores of the secondary instance have been halted in response to detecting, by the primary instance, that the secondary instance is in the fault or panic state.

6. The system of claim 1 , the operations further comprising recovering, by the primary instance, the plurality of CPU cores from the secondary instance using an Inter-processor Interrupt (IPI) start-up from the primary instance.

7. The system of claim 1 , wherein the secondary instance and the primary instance are communicatively coupled to a memory location shared between the primary instance and the secondary instance.

8. A method, comprising:
issuing, by a primary instance, a central processing unit (CPU) hotplug from a user space;
delivering, by the CPU hotplug, a non-maskable interrupt (NMI) to a bootstrap core;
initiating, by the NMI, a recovery sequence to switch a context of the bootstrap core from a secondary instance to the primary instance;
executing the bootstrap core into an online state in the primary instance; and
recovering, by the primary instance, a plurality of CPU cores from the secondary instance.

9. The method of claim 8 , wherein initiating, by the NMI, a recovery sequence to switch a context of the bootstrap core from a secondary instance to the primary instance comprises:
writing a trampoline page directory table address to a control register of the secondary instance; and
branching execution of the bootstrap core to a real mode machine start address of the primary instance.

10. The method of claim 9 , wherein branching the execution of the bootstrap core to the real mode machine start address of the primary instance is performed by leveraging an advanced power management (APM) restart hook.

11. The method of claim 8 , further comprising issuing, by the primary instance, the CPU hotplug from the user space in response to detecting, by the primary instance, that the secondary instance is in a fault or panic state.

12. The method of claim 11 , further comprising presuming that the plurality of CPU cores of the secondary instance have been halted in response to detecting, by the primary instance, that the secondary instance is in the fault or panic state.

13. The method of claim 8 , further comprising recovering, by the primary instance, the plurality of CPU cores from the secondary instance using an Inter-processor Interrupt (IPI) start-up from the primary instance.

14. The method of claim 8 , wherein the secondary instance and the primary instance are communicatively coupled to a memory location shared between the primary instance and the secondary instance.

15. One or more computer-readable non-transitory storage media embodying instructions that, when executed by a processor, cause performance of operations comprising, comprising:
issuing, by a primary instance, a central processing unit (CPU) hotplug from a user space;
delivering, by the CPU hotplug, a non-maskable interrupt (NMI) to a bootstrap core;
initiating, by the NMI, a recovery sequence to switch a context of the bootstrap core from a secondary instance to the primary instance;
executing the bootstrap core into an online state in the primary instance; and
recovering, by the primary instance, a plurality of CPU cores from the secondary instance.

16. The one or more computer-readable non-transitory storage media of claim 15 , wherein initiating, by the NMI, a recovery sequence to switch a context of the bootstrap core from a secondary instance to the primary instance comprises:
writing a trampoline page directory table address to a control register of the secondary instance; and
branching execution of the bootstrap core to a real mode machine start address of the primary instance.

17. The one or more computer-readable non-transitory storage media of claim 16 , wherein branching the execution of the bootstrap core to the real mode machine start address of the primary instance is performed by leveraging an advanced power management (APM) restart hook.

18. The one or more computer-readable non-transitory storage media of claim 15 , the operations further comprising issuing, by the primary instance, the CPU hotplug from the user space in response to detecting, by the primary instance, that the secondary instance is in a fault or panic state.

19. The one or more computer-readable non-transitory storage media of claim 18 , the operations further comprising presuming that the plurality of CPU cores of the secondary instance have been halted in response to detecting, by the primary instance, that the secondary instance is in the fault or panic state.

20. The one or more computer-readable non-transitory storage media of claim 15 , the operations further comprising recovering, by the primary instance, the plurality of CPU cores from the secondary instance using an Inter-processor Interrupt (IPI) start-up from the primary instance.

Assignees

• Cisco Tech Inc

Inventors

• Chandra Amit
• Lawrence Nivin
• Martineau Etienne

Classifications

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F9/4405

  Initialisation of multiprocessor systems · CPC title